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參數(shù)資料
| 型號： | TS83102G0BMGS |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | HERMATIC, CI-CGA-152 |
| 文件頁數(shù)： | 29/52頁 |
| 文件大?。?/td> | 1548K |
| 代理商： | TS83102G0BMGS |
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35
5360A–BDC–06/05
TS83102G0BMGS
However, the external TOD and TDR values can be dictated by the total digital data skews
between each TOD and TDR. These digital skews can include the MCM board, bonding wires
and output line length differences, as well as output termination impedance mismatches.
The external (on-board) skew effect has not been taken into account for the specification of TOD
and TDR minimum and maximum values.
9.1.4
Principle of Operation
The analog input is sampled on the rising edge of the external clock’s input (CLK/CLKB) after TA
(aperture delay). The digitized data is available after 4 clock periods’ latency (pipeline delay
[TPD]) on the clock’s rising edge, after a typical propagation delay TOD. The Data Ready differ-
ential output signal frequency (DR/DRB) is half the external clock’s frequency. It switches at the
same rate as the digital outputs. The Data Ready output signal (DR/DRB) switches on the exter-
nal clock’s falling edge after a propagation delay TDR.
If TOD equals TDR, the rising edge (True-False) of the differential Data Ready signal is placed
in the middle of the Output Data Valid window. This gives maximum setup and hold times for
external data acquisition.
A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is
available for initializing the differential Data Ready output signal (DR/DRB). This feature is man-
datory in certain applications using interleaved ADCs or using a single ADC with demultiplexed
outputs. Without Data Ready signal initialization, it is impossible to store the output digital data in
a defined order.
When used with Atmel’s TS81102G0 1:4/8 8/10 bit DMUX, it is not necessary to initialize Data
Ready, as this device can start on either clock edge.
9.2
Principle of Data Ready Signal Control by DRRB Input Command
9.2.1
Data Ready Output Signal Reset
The Data Ready signal is reset on the DRRB input command’s falling edge, on the ECL logical
low level (-1.8V). DRRB may also be tied to V
EE = - 5V for the Data Ready output signal master
reset. As long as DRRB remains at a logical low level, (or tied to V
EE = - 5V), the Data Ready
output remains at a logical zero and is independent of the external free-running encoding clock.
The Data Ready output signal (DR/DRB) is reset to a logical zero after TRDR.
TRDR is measured between the -1.3V point of the DRRB input command’s falling edge and the
zero crossing point of the differential Data Ready output signal (DR/DRB).The Data Ready
Reset command may be a pulse of 1 ns minimum time width.
9.2.2
Data Ready Output Signal Restart
The Data Ready output signal restarts on the DRRB command’s rising edge, on the ECL logical
high level (-0.8V).
DRRB may also be grounded, or may float, for normal free-running of the Data Ready output
signal. The Data Ready signal’s restart sequence depends on the logical level of the external
encoding clock, at a DRRB rising edge instant:
The DRRB’s rising edge occurs when the external encoding clock input (CLK/CLKB) is LOW
: the Data Ready output’s first rising edge occurs after half a clock period on the clock’s falling
edge, and a TDR delay time of 410 ps, as defined above.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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