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參數(shù)資料
| 型號(hào)： | TS83102G0BMGS |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | HERMATIC, CI-CGA-152 |
| 文件頁(yè)數(shù)： | 52/52頁(yè) |
| 文件大?。?/td> | 1548K |
| 代理商： | TS83102G0BMGS |
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9
5360A–BDC–06/05
TS83102G0BMGS
Notes:
1. Output error amplitude < ±6 LSB, Fs = 2 Gsps, TJ = 110°C
2. See ”Definition of Terms” on page 32.
3. 50
// C
LOAD = 2 pF termination (for each single-ended output). Termination load parasitic capacitance derating value:
50 ps/pF (ECL). See ”Timing Information” on page 34.
4. TOD and TDR propagation times are defined at package input/outputs. They are given for reference only. See ”Propagation
5. Values for TD1 and TD2 are given for a 2 Gsps external clock frequency (50% duty cycle). For different sampling rates, apply
the following formula: TD1 = T/2 + (|TOD - TDR|) and TD2 = T/2 + (|TOD - TDR|), where T = clock period. This places the ris-
ing edge (True/False) of the differential data ready signal in the middle of the output data valid window. This gives maximum
setup and hold times for external data acquisition.
Ringback
2%
Switching Performance and Characteristics
Maximum clock frequency (2)
FSMax
2
2.2
Gsps
Minimum clock frequency (2)
4FSMin
150
200
Msps
Minimum clock pulse width (high)
4
TC1
0.2
0.25
2.5
ns
Minimum clock pulse width (low)
4
TC2
0.2
0.25
2.5
ns
Aperture delay (2)
4
TA
160
ps
Aperture uncertainty (2)
4
Jitter
150
200
fs rms
Output rise/fall time for DATA (20 - 80%) (3)
4
TR/TF
150
200
ps
Output rise/fall time for DATA READY (20 - 80%) (3)
4
TR/TF
150
200
ps
Data output delay (4)
4
TOD
360
ps
Data ready output delay (4)
4
TDR
410
ps
4
ITOD
minus
TDRI
050
100
ps
Output data to data ready propagation delay (5)
4
TD1
250
300
350
ps
Data ready to output data propagation delay (5)
4
TD2
150
200
250
ps
Output data pipeline delay
4
TPD
4.0
Clock
cycles
Data ready reset delay
4
TRDR
1000
ps
3.6
Transient and Switching Performances
Parameter
Test
Level
Symbol
Min
Typ
Max
Unit
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相關(guān)代理商/技術(shù)參數(shù) |
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| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
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| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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