![](http://datasheet.mmic.net.cn/390000/TVP3030-175_datasheet_16839167/TVP3030-175_101.png)
C–1
Appendix C
PC-Board Layout Considerations
PC-Board Considerations
It is recommended that a four-layer PC board be used with the TVP3030 video interface palette: one layer
for 5-V power, one for GND, and two for signals. The layout should be optimized for the lowest noise on the
TVP3030 power and ground lines by shielding the digital inputs and providing good decoupling. The lead
length between groups of analog V
DD
and GND terminals (see Figure C–1) should be minimized so as to
minimize inductive ringing. The TVP3030 P0–P127 terminal assignments have been selected for minimum
interconnect lengths between these inputs and the standard VRAM pixel data outputs. The TVP3030 should
be located as close as possible to the output connectors to minimize noise pickup and reflections due to
impedance mismatch.
The analog outputs are susceptible to crosstalk from digital lines; digital traces must not be routed under
or adjacent to the analog output traces.
For maximum performance, the analog-video-output impedance, cable impedance, and load impedance
should be the same. The load resistor connection between the video outputs and GND should be as close
as possible to the TVP3030 to minimize reflections. Unused analog outputs should be connected to GND.
Analog output video edges exceeding the CRT monitor bandwidth can be reflected, producing cable-
length-dependent ghosts. Simple pulse filters can reduce high-frequency energy, thus reducing EMI and
noise. The filter impedance must match the line impedance.
Ground Plane
It is also recommended that only one ground plane be used for both the TVP3030 and the rest of the logic.
Separate digital and analog ground planes are not needed and can potentially cause system problems.
Power Plane
Split-power planes for the TVP3030 and the rest of the logic are recommended. The TVP3030 VIP analog
circuitry should have its own power plane, referred to as AV
DD
. These two power planes should be
connected at a single point through a ferrite bead, as shown in Figures C–1 and C–2.This bead should be
located as near as possible to where the power supply connects to the board. To maximize the
high-frequency power supply rejection, the video output signals should not overlay the analog power plane.
Supply Decoupling
The bypass capacitors should be installed using the shortest leads possible. This reduces the lead
inductance and is consistent with reliable operation.
For the best performance, a 0.1-
μ
F ceramic capacitor in parallel with a 0.01-
μ
F chip capacitor should be
used to decouple each of the groups of power terminals to GND. These capacitors should be placed as close
as possible to the device, as shown in Figure C–2.
If a switching power supply is used, the designer should pay close attention to reducing power supply noise
and consider using a three-terminal voltage regulator for supplying power to AV
DD
.