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參數(shù)資料
| 型號： | TVP3030-250 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器） |
| 文件頁數(shù)： | 35/107頁 |
| 文件大?。?/td> | 689K |
| 代理商： | TVP3030-250 |
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2–19
2.8
The TVP3030 offers a highly versatile multiplexing scheme as illustrated in Tables 2–17 through 2–21. The
multiplexing modes allow the pixel bus (P127–P0) to be programmed to 4, 8, 16, 24, or 32 bits/pixel with
pixel bus widths ranging from 8 to 128 bits. The use of on-chip multiplexing allows graphics systems to be
designed that can support multiple pixel depths and resolutions with no hardware modification. The
TVP3030 can also be configured for pseudo-color, direct-color, or true-color operation.
Multiplexing Modes of Operation
Multiplexing of the pixel bus is controlled by and programmed through the multiplex-control register and the
true-color control register. Table 2–16 details the register settings for each mode of operation.
2.8.1
The TVP3030 pixel bus supports both little- and big-endian data formats for all pseudo-color, direct-color,
and true-color modes of operation. The data-format selection is controlled by bit GCR3 of the general-control
register (see Section 2.16.1). When GCR3 is logic 0 (default), the format is set to little endian. When GCR3
is logic 1, the format is set to big endian.
Little-Endian and Big-Endian Data Format
In a big-endian design, the external VRAM data bus bits must be connected in reverse order to the TVP3030
pixel bus; i.e., D127 connected to P0, D0 connected to P127, etc. This connects the pixels to the P127–P0
bus in the correct order with the first pixel to be displayed on the LSBs of the P127–P0 bus. However, the
individual bits within each pixel are now connected in bit-reversed order. When big-endian format is
selected, this bit-reversed order of each pixel is compensated for internally. The bit-reversal of pixels takes
place in groups of 4, 8, 16, or 32 bits depending on the multiplexing mode selected. This scheme enables
big-endian systems to operate in all of the available color-depths including the packed-24 modes.
2.8.2
The VGA modes are used to emulate the VGA modes of most personal computers. The TVP3030 has two
configurations to support VGA modes: VGA mode 1 and VGA mode 2.
VGA Modes
VGA mode 1 allows the loop clock PLL to be used to align the received LCLK (and VGA data) with the internal
dot clock as a means of acheiving higher speed VGA operation. This mode applies only to systems which
do not use the TVP3030 SCLK output to drive the VRAM shift clock. Since the power-up default is VGA mode
2, software intervention is required to take advantage of VGA mode 1. To use VGA mode 1, bit MCR7 in
the multiplex control register must be logic 1 to select VGA mode and bit MCR6 must be logic 1 to cause
VGA7–VGA0 and the system video controls to be latched with LCLK. The clock selection register bits
CSR3–CSR0 are usually set to select the pixel clock PLL. The loop clock PLL must be output on the RCLK
terminal (MKC5 = logic 1).
The accelerator uses RCLK to clock its VGA controller and to generate the system video controls. The
accelerator outputs a clock that is a delayed (and possibly divided down) version of RCLK which connects
to the LCLK input of the TVP3030. The system video controls and VGA7–VGA0 are output synchronous
with LCLK. The loop clock PLL generates RCLK with the proper phase to synchronize VGA7–VGA0 and
LCLK with the TVP3030 internal clocks.
VGA mode 2 supports most graphics accelerators with integrated VGA and also supports add-on graphics
boards that receive the VGA pseudo-color data from a separate VGA controller via a feature connector. VGA
mode 2 is active at power-up and after reset and is fully functional without any software intervention. VGA
data and video controls are received with a synchronous VGA clock.
The feature connector configuration is emulated by many graphics accelerators with integrated VGA. In this
configuration, the pixel clock PLL is output on the RCLK terminal (MKC5 = logic 0) and sent to the
accelerator’s clock input. The clock output from the accelerator is connected to the CLK0 input of the
TVP3030. The loop clock PLL is not used and should be reset. The accelerator outputs the VGA video
controls and VGA7–VGA0 data synchronous with CLK0 and thereby emulates the feature connector
configuration. In VGA mode 2, the TVP3030 derives the dot clock from CLK0 and latches the VGA7–VGA0
data and VGA video controls using CLK0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3030-250MEP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3033 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175PPA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3033-220 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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