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參數(shù)資料
| 型號： | TVP3030-250 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器） |
| 文件頁數(shù)： | 21/107頁 |
| 文件大小： | 689K |
| 代理商： | TVP3030-250 |
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2–5
if the VGA port is used. This selects latching of VGA(7–0) and VGABL with CLK0. If CSR(2–0) = 000, CLK0
is also selected as the clock source to generate the internal dot clock. However, in this mode, MCR6 must
be logic 1 if the VGA port is used. This selects latching of VGA(7–0) and SYSBL with LCLK.
Additionally, two crystal oscillator terminals (XTAL1, XTAL2) are provided for the integrated pixel clock and
memory clock frequency synthesis PLLs. These terminals are intended for use with a quartz crystal
resonator, but a discrete oscillator can also be utilized and input on the XTAL2 terminal (XTAL1 terminal
should be left floating in this case).
Selection of the pixel clock PLL as the pixel clock source is performed by programming the clock selection
register.
Table 2–5. Clock-Selection Register Bits CSR(3–0) (Index: 0x1A, Access: R/W, Default: 0x07)
CLOCK SELECT
REGISTER BITS
FUNCTION
3
0
2
0
1
0
0
0
Select CLK0 as clock source (for use with LCLK latching of VGA port). See
Section 2.8.2.
0
0
0
1
Reserved
0
0
1
0
Reserved
0
0
0
0
1
1
1
0
0
1
0
1
Reserved
Reserved
Select pixel clock PLL as clock source
0
1
1
0
Disable internal dot clock for reduced power consumption
0
1
1
1
Select CLK0 as clock source (for use with CLK0 latching of VGA port). See
Section 2.8.2.
1
X
X
X
Reserved
2.5
In addition to externally supplied clock sources, the TVP3030 has three on-chip, fully programmable,
frequency-synthesis phase-locked loops (PLLs). The first (pixel clock) PLL is intended for pixel clock
generation for frequencies up to the device limit. The second (MCLK) PLL is provided for general clocking
such as the system clock or memory clock, and the third PLL (called the loop clock PLL) is provided for
synchronizing pixel data and latch timing by compensating for system loop delay.
PLL Clock Generators
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3030-250MEP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3033 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175PPA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3033-220 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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