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參數(shù)資料
| 型號： | TVP3030-250 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器） |
| 文件頁數(shù)： | 31/107頁 |
| 文件大?。?/td> | 689K |
| 代理商： | TVP3030-250 |
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2–15
2.6.2
For those systems where the color palette data latch clock (LCLK) and VRAM shift clock are generated by
the graphics controller, the TVP3030 SCLK output is not utilized. In these systems, RCLK should be
connected to the graphics controller to provide the timing reference for pixel data and video control signals.
LCLK should be a delayed version of RCLK such that the pixel data and video control signals meet the setup
and hold requirements relative to the rising edge of LCLK. LCLK may be a frequency-divided and delayed
version of RCLK, as long as linear phase changes in RCLK produce linear phase changes in LCLK (and
the pixel data). Bit TCR5 in the true-color control register must be logic 0 if SCLK is not being used, so that
additional pipeline delay in the video controls is not inserted.
Frame Buffer Timing Without Using SCLK
The first LCLK rising edge out of blank latches the first pixel group. The last LCLK rising edge during blank
latches the last pixel group. Figure 2–5 shows typical frame buffer timing for this case. In Figure 2–5, the
delay from RCLK to SYSBL and P127–P0 will depend on the total system loop delay through the graphics
accelerator and the VRAM. This delay may be as long as is required. It need not be less than the RCLK cycle
time.
2nd
Group
3rd
Group
4th
Group
Last Group of Pixel Data
RCLK
SYSBL
P(127–0)
Latch Last Group of Pixel Data
and SYSBL High
Latch First Group of Pixel Data
and SYSBL High
LCLK
1st
Group
Figure 2–5. Frame Buffer Timing Without Using SCLK
2.6.3
The SCLK signal which is generated by the TVP3030 may be directly connected to VRAM, providing the
shift clock to clock data from VRAM into the pixel input port. The RCLK signal must be used as the timing
reference to clock pixel data into this port. Therefore, when SCLK is used, RCLK is typically directly tied back
to LCLK, or LCLK can be a delayed version (buffered) of RCLK within the timing requirements of the
TVP3030.
Frame Buffer Timing Using SCLK
Operation using the SCLK timing mode must limit the RCLK-to-LCLK loop delay to the specified maximum
delay. This ensures that the relationship between the end of blank and the first SCLK plulse is not disturbed.
If SCLK is not used, the RCLK to SCLK delay may be as long as is needed by system logic. Figure 2–6
illustrates the frame buffer timing using SCLK.
相關(guān)PDF資料 |
PDF描述 |
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| TVP3409-170 | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| TVP3409-135 | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| TVP3703-170 | Video Interface PALETTE Exract(雙PLL，先進的視頻接口調(diào)色器) |
| TVP3703-135 | Video Interface PALETTE Exract(雙PLL，先進的視頻接口調(diào)色器) |
| TVP3703FN | VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3030-250MEP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3033 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175PPA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3033-220 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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