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參數(shù)資料
| 型號(hào)： | TVP3030-250 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器） |
| 文件頁數(shù)： | 26/107頁 |
| 文件大?。?/td> | 689K |
| 代理商： | TVP3030-250 |
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2–10
2.5.2.1
The MCLK is normally used as the graphics controller system clock and memory clock. During
reprogramming of the PLLs, a wide range of unpredictable frequencies are generated as the PLL transitions
to the new programmed frequency. These transition effects can produce unwanted results in some systems.
The TVP3030 provides a mechanism for smooth transitioning of the MCLK PLL. The following programming
steps are recommended.
Changing the MCLK Frequency
1.
Program the pixel clock PLL to the same frequency to which MCLK will be changed, and poll the
pixel clock PLL status until the LOCK bit is logic 1.
2.
Select the pixel clock PLL as the dot clock source if it is not already selected.
3.
Switch to output dot clock on the MCLK terminal by writing bits MKC4, MKC3 to 0,0 followed by
0,1 in MCLK/loop clock control register.
4.
Program the MCLK PLL for the new frequency and poll the MCLK PLL status until the LOCK bit
is logic 1.
5.
Switch to output MCLK on the MCLK terminal by writing bits MKC4, MKC3 to 1,0 followed by 1,1
in MCLK control register.
6.
2.5.3
Many of the current high performance graphics accelerators with built in VGA support generate their own
VRAM shift clock and pixel data latching clock (LCLK) as discussed in Section 2.6.2. As stated before, the
TVP3030 provides an RCLK timing reference output to be used by the graphics controller to generate these
signals. A common industry problem exists, however, in that the delay through the loop (i.e., from RCLK
through the controller to produce LCLK and pixel data) may be greater than the RCLK cycle time minus setup
time. It then becomes very difficult to resynchronize the rising edges of the LCLK signal to the internal dot
clock within the specified timing requirements. Variations in graphics accelerator propagation delays from
device to device can cause severe production problems at the board level. The TVP3030 incorporates a
unique loop clock PLL circuit to maintain a valid LCLK/dot clock phase relationship and ensure that proper
LCLK and pixel data setup timing is met, regardless of the amount of system loop delay.
Loop Clock PLL
After device reset, the loop clock PLL provides the dot clock frequency to the RCLK output multiplexer.
However, the RCLK output multiplexer will ignore the loop clock PLL output and instead pass the pixel clock
PLL output to the RCLK terminal, which provides a reference clock to the VGA controller. In this configuration
(VGA mode 2), the VGA controller returns VGA data and video controls along with a synchronous clock that
becomes the TVP3030 dot clock source via CLK0. The PLLSEL(1,0) lines select either the 25.057 MHz or
28.636 MHz VGA frequencies.
Figure 2–2 illustrates the pixel data latching structure and the operation of the loop clock PLL. The selected
clock source is used to generate the dot clock which drives most of the digital logic of the TVP3030. The
dot clock is used as a reference frequency by the loop clock PLL and is subdivided as specified by the
N value register. The incoming LCLK is used as the other input of the PLL and is subdivided as specified
by the M value register. The PLL generates RCLK with the proper frequency and phase shift to phase align
the divided dot clock and divided LCLK. The pixel bus is latched on the rising edge of LCLK and then aligned
with the internal dot clock to synchronize with internal logic.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3030-250MEP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3033 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175PPA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3033-220 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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