參數(shù)資料
型號： TVP3030-250
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器）
文件頁數(shù)： 41/107頁
文件大?。?/td> 689K
代理商： TVP3030-250
2–25
Table 2–16. Multiplex Mode and Bus-Width Selection (Continued)
DATA
BITS
PER
PIXEL
(see
Note 1)
0x18)
MODE
TABLE
REFERENCE
(see
Note 3)
OVERLAY
BITS
PER
PIXEL
MULTI-
PLEX
RATIO
(see
Note 2)
PIXEL
BUS
WIDTH
MULTIPLEX-
CONTROL
REGISTER
(INDEX
0x19)
TRUE-
COLOR-
CONTROL
REGISTER
(INDEX
SUB-
MODE
Direct-
Color
1
0x16
0x5B
24
32
4:3
NA
d1
0x16
0x5C
24
64
8:3
NA
d2
Packed-24
Packed 24
R-G-B
8 8 8
8–8–8
0x16
0x5D
24
128
16:3
NA
d3
0x1E
0x5B
24
32
5:4
NA
d4
0x1E
0x5C
24
64
5:2
NA
d5
0x1E
0x5D
24
128
5:1
NA
d6
2
0x17
0x5B
24
32
4:3
NA
d7
0x17
0x5C
24
64
8:3
NA
d8
Packed-24
Packed 24
B-G-R
8 8 8
8–8–8
0x17
0x5D
24
128
16:3
NA
d9
0x1F
0x5B
24
32
5:4
NA
d10
0x1F
0x5C
24
64
5:2
NA
d11
0x1F
0x5D
24
128
5:1
NA
d12
3
0x06
0x5B
24
32
1
8
d13
32-Bit
O R G B
O-R-G-B
0x06
0x5C
24
64
2
8
d14
0x06
0x5D
24
128
4
8
d15
4
0x07
0x5B
24
32
1
8
d16
32-bit
B G R O
B-G-R-O
0x07
0x5C
24
64
2
8
d17
0x07
0x5D
24
128
4
8
d18
5
0x05
0x52
16
16
1
NA
d19
16-bit XGA
16 bit XGA
R-G-B
5 6 5
5–6–5
0x05
0x53
16
32
2
NA
d20
0x05
0x54
16
64
4
NA
d21
0x05
0x55
16
128
8
NA
d22
6
16 bi
16-bit
TARGA
O-R-G-B
O R G B
1–5–5–5
0x04
0x52
15
16
1
1
d23
0x04
0x53
15
32
2
1
d24
0x04
0x54
15
64
4
1
d25
0x04
0x55
15
128
8
1
d26
NOTES:
1. Data bits per pixel is the number of bits of pixel information used as color data for each displayed pixel,
often referred to as the number of bit planes.
2. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each
LCLK (load clock) pulse. For example, with a 64-bit pixel bus width and 8 bit planes, each bus load is
comprised of 8 pixels. The RCLK frequency must be chosen as a function of the multiplex mode selected
and any frequency division provided by the controller. The RCLK frequency is not automatically set by
mode selection; it must be set by programming the loop clock PLL registers.
3. This column is a reference to Tables 2–17 through 2–21, where the actual manipulation of pixel
information and pixel latching sequences are illustrated for each of the multiplexing modes.
相關PDF資料
PDF描述
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進的視頻接口調(diào)色器)
TVP3703-135 Video Interface PALETTE Exract(雙PLL，先進的視頻接口調(diào)色器)
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