參數(shù)資料
型號(hào): TVP3409-170
廠商: Texas Instruments, Inc.
英文描述: Advanced Video Interface PALETTE(雙PLL,視頻接口調(diào)色器真彩色CMOS)
中文描述: 先進(jìn)的視頻接口盒(雙鎖相環(huán),視頻接口調(diào)色器真彩色的CMOS)
文件頁數(shù): 13/57頁
文件大?。?/td> 312K
代理商: TVP3409-170
2–1
2 Detailed Description
The TVP3409 RAMDAC is compatible with the architecture of the ATT20C499 and ATT20/21C498
RAMDACs. The TVP3409 contains 24-bit packed pixels on a 16-terminal interface. The device includes
dual clock synthesizers which can synthesize a pixel clock and a memory clock from a reference frequency.
The device includes a third analog PLL for pixel clock multiplication. Multiplication of 2
clock is set automatically when certain color modes are programmed. Clock synthesis and clock
multiplication reduce the maximum clock speed on the board. The reduced clock speed eases high-speed
board design and FCC certification. Table 2–1 lists the feature comparisons and functional differences
between the TVP3409/ATT20C409, the ATT20C499, and the ATT21C498 RAMDACs.
or 2/3
the pixel
The TVP3409 has been designed to allow a single board layout for assembly using either the TVP3409 or
other industry standard 44-terminal PLCC RAMDAC.
The TVP3409 includes simple indexed addressing of all control, test, and identification registers using only
two register select terminals. This supplements multiple accesses of the pixel read mask register (RMR)
used in this and other devices.
A 14.318 MHz crystal connects across the XIN and XOUT terminals when using the clock synthesizer (see
Section 1.4, System Block Diagram). Other input crystal frequencies can be used. When using a reference
frequency instead of a crystal, the signal connects to XIN and XOUT floats (disconnected).
Table 2–1. Feature Comparisons and Functional Differences of the TVP3409/ATT20C409,
ATT21C498, and ATT20C499
FEATURE
TVP3409/ATT20C409
ATT20C499
ATT21C498
Pixel interface
16 terminals
24 terminals
16 terminals
Packed 24-bit pixels
Yes
Yes
Yes
Clock synthesizers
Dual
Dual
No
Clock multiplication factors
2, 0.67 PCLK (analog)
2, 0.67 PCLK
(analog)
2x (digital)
Multiplexer rate for 8-bit pixels
2:1
2:1
2:1
Color modes
9
13
11
Software compatible to ATT20C498
Yes
Yes
Yes
Control registers
CR(1,0), CC0
CR(1,0), CC0
CR0
Clock synthesizer A register set A
Read/write access:
AA, AB
AC, AD
None
Read/Write
Read
Read/Write
N/A
Clock synthesizer B register set B
Read/write access:
BA, BB
BC,
BD
None
None
Read/Write
Read
Read/Write
Read/Write
N/A
MSW Terminal
No
Yes
Yes
Package
68 PLCC
68 PLCC
44 PLCC
Manufacturer identification register (MIR) value
MIR = 0x97
MIR = 0x84
MIR = 0x84
Device identification register (DIR) value
DIR = 0x09
DIR = 0x99
DIR = 0x98
Revision identification
No
No
No
Maximum speed (MHz)
170
170
170
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