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參數(shù)資料
| 型號： | TVP3409-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| 中文描述： | 先進的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS） |
| 文件頁數(shù)： | 22/57頁 |
| 文件大?。?/td> | 312K |
| 代理商： | TVP3409-170 |
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2–10
The clock synthesizer B register sets are operational on power up. They can be read from or written to by
the MPU at any time. All of the registers are reset to produce the frequencies in Table 2–19 upon asserting
RESET. To read from or write to these registers, set bit CR0(0) = 1, write 0x60–0x6F to the WMA, and set
RS(1,0) = HL. These registers can be accessed by indexed addressing (see Table 2–5).
Table 2–13. Clock Synthesizer B Parameters
REGISTER
CONTROL SET
ACCESS
REGISTER
NUMBER
DESCRIPTION
DEFAULT
FREQUENCY
Reserved
A
None
0
29 979 MH
29.979 MHz
Reserved
CC(1,0) = 00 or
FS(1,0) = LL
B
1
Reserved
1
Reserved
None
0
40 091 MH
40.091 MHz
Reserved
CC(1,0) = 01 or
FS(1,0) = LH
C
1
Reserved
1
Reserved
None
0
50 114 MH
50.114 MHz
Reserved
CC(1,0) = 10 or
FS(1,0) = HL
D
1
Reserved
1
BD0(7–0)
Read or
Write
0
Feedback divider term (M)
59 957 MH
59.957 MHz
BD1(7,6)
CC(1,0) = 11 or
FS(1,0) = HH
1
Postscaler divider term (P)
BD1(5–0)
1
Reference divider term (N)
Table 2–14. Clock Synthesizer B Register Set Fields
CLOCK REGISTER 0, BITS AND FIELDS
CLOCK REGISTER 1, BITS AND FIELDS
7
6
5
4
M(7–0)
3
2
1
0
7
P(1,0)
6
5
4
3
N(5–0)§
2
1
0
CLOCK REGISTER 2, BITS AND FIELDS
CLOCK REGISTER 3, BITS AND FIELDS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Reserved
Reserved
M(7–0), 8 bits, integer from 0 to 255 (2 is added to this value)
P(1,0), 2 bits, integer from 0 to 3 (these bits indicate the power of 2)
§N(5–0), 6 bits, integer from 0 to 63 (2 is added to this value)
2.3
The following information describes how the RAMDAC operates after the RESET terminal has been toggled
low.
Reset State
When RESET is asserted, OTCLKA outputs 25.057 MHz (VGA graphics frequency), 28.189 MHz (VGA text
frequency), 50.114 MHz, or 75.170 MHz depending on the values of the frequency select terminals FS(1,0)
or the clock synthesizer control register bits CC(5,4) (see Table 2–19).
When RESET is asserted, OTCLKB outputs 29.979, 40.091, 50.114, or 59.957 MHz depending on the
values of the frequency select terminals FS(1,0) or the clock synthesizer control register bits CC(1,0).
During normal operation, the clock synthesizers can be programmed to any frequency within the capability
of the device. The clock synthesizers can be powered down and the outputs are then 3-stated.
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| TVP3409-170CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| TVP3703 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
| TVP3703-135CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3703FN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
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