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參數(shù)資料
| 型號： | TVP3409-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| 中文描述： | 先進的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS） |
| 文件頁數(shù)： | 15/57頁 |
| 文件大?。?/td> | 312K |
| 代理商： | TVP3409-170 |
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2–3
Table 2–5. Indexed Clock Synthesizer Configuration Registers (see Notes 1, 2, and 3)
REGISTER
INDEXED
ACCESS
CR0(0) = 1
REGISTER ADDRESSED BY MPU
DESCRIPTION
AA0
0x40
Reserved
Reserved
AA1
0x41
Reserved
Reserved
AA2
0x42
Reserved
Reserved
AA3
0x43
Reserved
Reserved
AB0
0x44
Reserved
Reserved
AB1
0x45
Reserved
Reserved
AB2
0x46
Reserved
Reserved
AB3
0x47
Reserved
Reserved
AC0
0x48
Clock A control register 0 of set C
Feedback divider (M)
AC1
0x49
Clock A control register 1 of set C
Reference (N) and postscaler (P) dividers
AC2
0x4A
Clock A control register 2 of set C
Reserved
AC3
0x4B
Clock A control register 3 of set C
Reserved
AD0
0x4C
Clock A control register 0 of set D
Feedback divider (M)
AD1
0x4D
Clock A control register 1 of set D
Reference (N) and postscaler (P) dividers
AD2
0x4E
Clock A control register 2 of set D
Reserved
AD3
0x4F
Clock A control register 3 of set D
Reserved
—
0x50–0x5F
Reserved
Reserved
BA0
0x60
Reserved
Reserved
BA1
0x61
Reserved
Reserved
BA2
0x62
Reserved
Reserved
BA3
0x63
Reserved
Reserved
BB0
0x64
Reserved
Reserved
BB1
0x65
Reserved
Reserved
BB2
0x66
Reserved
Reserved
BB3
0x67
Reserved
Reserved
BC0
0x68
Reserved
Reserved
BC1
0x69
Reserved
Reserved
BC2
0x6A
Reserved
Reserved
BC3
0x6B
Reserved
Reserved
BD0
0x6C
Clock B control register 0 of set D
Feedback divider (M)
BD1
0x6D
Clock B control register 1 of set D
Reference (N) and postscaler (P) dividers
BD2
0x6E
Clock B control register 2 of set D
Reserved
BD3
0x6F
Clock B control register 3 of set D
Reserved
—
0x70–0x7F
Reserved
Reserved
NOTES:
1. RS1 = 1 and RS0 = 0
2. Access = R/W
3. For RMR reads CR0(0) = 0 is not applicable.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TVP3703-135CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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