參數(shù)資料
型號: TVP3409-170
廠商: Texas Instruments, Inc.
英文描述: Advanced Video Interface PALETTE(雙PLL,視頻接口調(diào)色器真彩色CMOS)
中文描述: 先進(jìn)的視頻接口盒(雙鎖相環(huán),視頻接口調(diào)色器真彩色的CMOS)
文件頁數(shù): 26/57頁
文件大?。?/td> 312K
代理商: TVP3409-170
2–14
2.6.3.1
Mode 0 displays data formatted in 8-bit pseudocolor. Mode 0 is selected by setting control register 0 bits
CR0(7–4) to 0000. Mode 0 ignores the P(15–8) inputs (see Figure 2–2).
Mode 0
2.6.3.2
Mode 1 displays data formatted for 15-bit per pixel true color (5–5–5). It is selected by setting control register
0 bits CR0(7–4) to 0001. Mode 1 uses all P(15–0) inputs.
Mode 1
2.6.3.3
Mode 2 accepts two 8-bit pseudocolor pixels on each clock. It is selected by setting control register bits
CR0(7–4) to 0010. The internal clock doubler outputs the pixels at twice the PCLK frequency. This allows
the RAMDAC to output 8-bit pseudocolor pixels at 135 MHz with 67.5 MHz data rates. Mode 2 uses all
P(15–0) inputs.
Mode 2
2.6.3.4
Mode 3 formats data in 16-bit per pixel true color (5–6–5). It is selected by setting control register 0 bits
CR0(7–4) to 0011. Mode 3 uses all P(15–0) inputs (see Figure 2–2).
Mode 3
2.6.3.5
Mode 4 accepts data formatted as 8-bit pseudocolor latched by two pixel clocks as 4-bit nibbles. Latching
two nibbles allows backward compatibility to previous RAMDACs. It is selected by setting control register
0 bits CR0(7–4) to 0100. Mode 4 ignores the P(15–4) inputs.
Mode 4
2.6.3.6
Mode 5 accepts a 24-bit pixel formatted as two 16-bit words latched by two pixel clocks. This is not a packed
mode. On the second pixel clock the upper byte is ignored. It is selected by setting control register 0 bits
CR0(7–4) to 0101. Mode 5 uses all P(15–0) inputs.
Mode 5
2.6.3.7
In mode 6, the 16-bit (5–6–5) pixel is latched in two bytes with two PCLKs. Latching one byte per clock allows
backward compatibilty to previous RAMDACs. Mode 6 is selected by setting control register 0 bits CR0(7–4)
to 0110. BLANK going high signals that the first pixel information is available on P(15–0). The rising edge
of PCLK captures BLANK going high and also captures the LSBs of the pixel information. The LSBs are
latched first followed by the MSBs. The LSBs and MSBs follow in succession until BLANK goes low. The
LSBs of the DACs are set to logical 0. Mode 6 ignores the P(15–8) inputs.
Mode 6
2.6.3.8
In mode 7 the 24-bit pixel is latched in three bytes with three PCLKs. Mode 7 is selected by setting the control
register 0 bits CR0(7–4) to 0111. The pixel information is collected over three rising edges of the pixel clock.
BLANK going high signals that the first pixel information is available on P(7–0). P(15–8) are ignored. The
rising edge of PCLK that captures BLANK going high also captures the blue information of the first pixel.
The blue pixel is latched first followed by the green pixel and red pixel. Blue, green, and red follow in
succession until BLANK goes low. Mode 7 ignores the P(15–8) inputs.
Mode 7
2.6.3.9
Reserved
Modes 8 – 13
2.6.3.10 Mode 14
Mode 14 formats data in packed 24-bit per pixel true color (2 pixels for three pixel clocks) using P(15–0)
terminals. BGR data (24-bit) are latched every 1 1/2 pixel clocks or two 24-bit pixels every three pixel clocks.
The external clock is multiplied by 2/3 by an internal multiplier. Mode 14 is selected by setting control register
0 bits CR0(7–4) to 1110. Mode 14 uses all P(15–0) inputs (see Figure 2–3).
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