![](http://datasheet.mmic.net.cn/390000/TVP3409-170_datasheet_16839170/TVP3409-170_16.png)
2–4
2.2
The TVP3409 is designed to support enhanced features in a VGA-compatible architecture. A typical VGA
system only supports RS0 and RS1 register select signals. With two register select lines, access to four
registers is provided (see Table 2–2). In order to provide enhanced features, additional register locations
are required (see Table 2–4 and Table 2–5) in the VGA-accessible register space.
Internal Register Set
To provide additional registers, two more addressing schemes have been added. The first scheme uses a
back door. The back door provides access to a control register (CR0), a manufacturer’s identification
register (MIR), and a device identification register (DIR). The back door is opened by sequential reads to
the pixel read mask register (RMR). The pixel read mask register was chosen because it is not often used
in normal VGA operation.
The second method is indirect indexed addressing. Indexed addressing can be used to access the RMR,
CR0 (when CR0(0) = 1), MIR, DIR, TST, CR1, CC and the registers in Table 2–5. Indexed addressing is the
only way to read or write CR1, CC, and the registers in Table 2–5.
To use this method, set CR0(0) = 1 using the back door (multiple accesses to the RMR). Write the address
register (WMA) with the address of the register to be read or written. The index of the registers accessible
indirectly are listed in the indexed access column in Tables 2–4 and 2–5. Perform a read or write operation
when RS(1,0) = 10. The value is read from or written to the register indexed by the contents of the address
register.
2.2.1
Write-Mode Address Register (WMA)
This register holds an 8-bit value that is used as an index when writing to the look-up table (LUT) data register
or extended indexed registers. For the LUT data register, this register points to one of the 256 RAMDAC
color RAM locations. Each of the RAMDAC color RAM locations are 24-bits wide (8-bits read, 8-bits green
and 8-bit blue). To write all 24-bits of a RAMDAC color RAM location, three successive writes are made to
the same address. After the sequence of three writes is completed, the 24-bit value is transferred to the
RAMDAC color RAM.
The LUT and RMR registers listed in Table 2–6 apply only in the 8-bit modes.
Table 2–6. Standard Register Set
REGISTER
REGISTER
TYPE
7
6
5
4
3
2
1
0
WMA
Read
Write
A7
A6
A5
A4
A3
A2
A1
A0
LUT
Read
Write
D7
D6
D5
D4
D3
D2
D1
D0
RMR
Read
Write
M7
M6
M5
M4
M3
M2
M1
M0
RMA
Read
Write
A7
A6
A5
A4
A3
A2
A1
A0
This register is only used while writing to the LUT data register or reading or writing the extended indexed
registers. After this register is set to the desired index, MPU data can be written to the LUT data register or
register values can be written to extended indexed registers. The WMA register is autoincrementing when
writing to the LUT. When three writes to the LUT data register are complete, the LUT data register data is
written to the RAMDAC color RAM and the WMA register increments by one. For this reason, the WMA
should be written every time extended indexed registers are accessed.
2.2.2
Read-Mode Address Register (RMA)
This register holds an 8-bit value that is used as an index when reading from the LUT data register or reading
or writing the extended indexed registers. To read all 24-bits of a RAMDAC color RAM location, three
successive reads are made to the same address.