![](http://datasheet.mmic.net.cn/390000/TVP3409-170_datasheet_16839170/TVP3409-170_31.png)
2–19
2.6.6
MPU Interface
The TVP3409 supports a standard MPU interface, allowing the MPU direct access to the write-mode
address register (WMA), look-up table data register (LUT), pixel read mask register (RMR), or read-mode
address register (RMA). As outlined in Table 2–2, the RS(1,0) select inputs indicate whether the MPU is
accessing the WMA, LUT, RMR, or RMA. To eliminate the requirement for external address multiplexers,
an 8-bit address register addresses the RAMDAC color RAM.
An address register can also be used as an indexed address to access the extended registers inside the
TVP3409. For indexed addressing, CR0(0) = 1, RS(1,0) = HL and the RMR becomes the indexed data
register.
2.6.6.1
Writing the RAMDAC LUT
The MPU writes the WMA register with the address of the RAMDAC color RAM location to be modified.
Using RS(1,0) to select the LUT, the MPU completes three continuous write cycles (6 or 8 bits each of red,
green, and blue). Following the blue write cycle, the 3 bytes of color information are concatenated into an
18- or 24-bit word and written to the location specified by the WMA register. The WMA register advances
to the next RAMDAC color RAM location which the MPU can modify by simply writing another sequence
of red, green, and blue data. A block of color values in successive locations can be written to by writing the
start address and performing continuous R, G, and B write cycles until the entire block has been written.
2.6.6.2
Reading the RAMDAC LUT
The MPU loads the RMA register with the address of the RAMDAC color RAM location to be read. The
contents of the RAMDAC color RAM at the address specified by the RMA register are copied into the LUT
register, and the RMA register advances to the next RAMDAC color RAM location. Using RS(1,0) to select
the LUT, the MPU completes three continuous read cycles (6 or 8 bits each of red, green, and blue). After
the blue read cycle, the contents of the RAMDAC color RAM at the address specified by the RMA register
are copied into the LUT register, and the RMA register advances to the next address. A block of color values
in successive locations can be read by writing the start address and performing continuous R, G, and B read
cycles until the entire block has been read.
2.6.6.3
Additional Information
Following a blue read or write cycle to color RAM location 0xFF, the address register resets to 0x00.
Operation of the MPU interface occurs asynchronously to the pixel clock. Internal logic synchronizes data
transfers between the RAMDAC color RAM and the LUT register. The transfers occur between MPU
accesses. As a result, the WR and RD signals must maintain a logic high for several clock cycles. See
Section 3.5.3, Microprocessor Port for the RD and WR pulse duration times. To eliminate sparkling on the
CRT screen during a MPU access to the RAMDAC color RAM, internal logic maintains the previous output
color data on the analog outputs while the transfer between RAMDAC color RAM and the LUT register
occurs.
To monitor the red, green, and blue read/write cycles, the address register has two additional bits AD(a) and
AD(b) that count modulo 3, as shown in Table 2–20. They are reset to 0 when the MPU writes to the address
register (WMA or RMA) and are not reset to 0 when the MPU reads the address register. The MPU does
not have access to these bits.
Table 2–20. Modulo 3 Counter Operation
AD(b,a)
ADDRESSED BY MPU
00
Red color RAM byte
01
Green color RAM byte
10
Blue color RAM byte