參數(shù)資料
型號(hào)： TVP5020TQFP
廠商： Texas Instruments, Inc.
英文描述： NTSC/PAL VIDEO DECODER
中文描述： NTSC / PAL視頻解碼器
文件頁數(shù)： 28/87頁
文件大小： 387K
代理商： TVP5020TQFP
2–14
into a wait state. Data transfer continues when the slave is ready for another byte of data and releases the
clock line (SCL).
Data transfer with acknowledge is necessary. The master generates an acknowledge related clock pulse.
The master releases the SDA line high during the acknowledge clock pulse. The slave pulls down the SDA
line during the acknowledge clock pulse so that it remains stable low during the high period of this clock
pulse.
When a slave does not acknowledge the slave address, the data line is left high. The master then generates
a stop condition to abort the transfer.
If a slave acknowledges the slave address, but some time later in the transfer cannot receive any more data
bytes, the master again aborts the transfer. The slave indicates a not ready condition by generating the not
acknowledge. The slave leaves the data line high and the master generates the stop condition.
If a master-receiver is involved in a transfer, it indicates the end of data to the slave-transmitter by not
generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must
release the data line to allow the master to generate a stop or repeated start condition.
2.6.2
I
2
C Write Operation
Data transfers occur using the following illustrated formats.
The I
2
C master initiates a write operation to the TVP5020 by generating a start condition followed by the
TVP5020’s I
2
C address (101110X). The address is in MSB first bit order followed by a 0 to indicate a write
cycle. After receiving a TVP5020 acknowledge, the I
2
C master sends a subaddress of the register or the
block of registers where it will write. Following the subaddress is one or more bytes of data, with MSB first.
The TVP5020 acknowledges the receipt of each byte upon completion of each transfer. The I
2
C master ends
a write operation by generating a stop condition.
The X in the address of the TVP5020 is 0 when the I
2
CA terminal is low and the X is 1 when the I
2
CA is high.
If the read or write cycle contains more than one byte, the internal subaddress does not increment
automatically.
0
I2C Start (Master)
S
7
6
5
4
3
2
1
0
I2C General address (Master)
1
0
1
1
1
0
X
0
9
I2C Acknowledge (Slave)
A
7
6
5
4
3
2
1
0
I2C Write register address (Master)
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
9
I2C Acknowledge (Slave)
A
7
6
5
4
3
2
1
0
I2C Write data (Master)
Data
Data
Data
Data
Data
Data
Data
Data
9
I2C Acknowledge (Slave)
A
0
I2C Stop (Master)
P
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