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參數(shù)資料
| 型號： | TVP5020TQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | NTSC/PAL VIDEO DECODER |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 50/87頁 |
| 文件大?。?/td> | 387K |
| 代理商： | TVP5020TQFP |
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2–36
Table 2–13. Dummy Timing Ancillary Data Sequence
BYTE
NO.
MSB
7
6
0
5
0
4
0
3
0
2
0
1
0
LSB
0
DESCRIPTION
1
0
0
2
1
1
1
1
1
1
1
1
Ancillary data preamble
3
1
1
1
1
1
1
1
1
4
NEP
EP
0
1
0
DID2
DID1
DID0
Data ID
5
1
0
0
0
0
0
0
0
Secondary data ID
6
1
0
0
0
0
0
0
0
Number of 32-bit data words
In the tables above, EP is even parity on the lower 6 bits and NEP is negated even parity. The checksum
for teletext data blocks is the 8 LSB’s of the sum of the data bytes. The data ID byte provides timing
information. Table 2–14 shows the possible values of the data ID byte and their meanings.
Table 2–14. Ancillary Data ID
DATA ID
EVENT IN SOURCE STREAM
DATA TYPE
50
Start of first, odd field
Dummy timing block
91
Sliced data of lines 1–23 of first field
VBI data
92
End of nominal VBI of first field, line 23
Dummy timing block
53
Sliced data of line 24 to end of first field
Full field teletext data
94
Start of second, even field
Dummy timing block
55
Sliced data of lines 1–23 of second field
VBI data
56
End of nominal VBI of second field, line 23
Dummy timing block
97
Sliced data of line 24 to end of second field
Full field teletext data
A dummy timing block will be inserted into the video stream during the horizontal blanking period following
line 23 of each field. If teletext data is available from line 23 it will be inserted into the video stream prior to
the dummy timing block.
2.14 Reset
Reset is initiated at power up or any time the RSTINB terminal is brought low. Table 2–15 describes the
status of the terminals on the TVP5020 during and immediately after reset. Following a powerup reset, the
host downloads microcode to the program memory of the TVP5020 for use by the internal microprocessor.
Table 2–15. Power-Up Reset Sequence
SIGNAL NAMES
DURING RESET
AFTER RESET
RSTINB, OEB, EXT_DATA_8
In
In
GLCO, PALI, FID, GPCL
In
Out
UV[7:0]
In
High-impedance
SCLK, PCLK, PREF
High-impedance
Out
Y[7:0], HSYN, VSYN, AVID
High-impedance
High-impedance
Host interface terminals: VC0, VC1, VC2, VC3, INTREQ, A1:0, D7:0
High-impedance
Active
Signals take their reset values during power up and anytime the RSTINB terminal is low.
The active state of the host interface terminals may be input, output, or input/output depending on the host
mode selected during reset.
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