參數(shù)資料
型號(hào)： TVP5020TQFP
廠(chǎng)商： Texas Instruments, Inc.
英文描述： NTSC/PAL VIDEO DECODER
中文描述： NTSC / PAL視頻解碼器
文件頁(yè)數(shù)： 39/87頁(yè)
文件大小： 387K
代理商： TVP5020TQFP
2–25
No Latency Read Phase 2:
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(to TVP5020)
7
0
6
1
5 4 3
1 0 0
2
0
1
1
0
1
7
A A A A A A A A D D D D D D D D
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
No Latency Read Phase 2
2.7.3.3
FIFO Status 0 Register
FIFO status 0 register returns two bits that report status and six unused bits.
7
6
5
4
3
2
1
0
FIFO Status 0
Undefined
Undefined
Undefined
DREQA
Undefined
Undefined
Undefined
VIRQ
DREQA: DMA request for FIFO A. This bit is the same as the teletext threshold bit (bit 1 of the interrupt status
register at VIP address1C0).
VIRQ: this bit returns the status of the INTREQ terminal. Reading this register does not clear this terminal.
COMMAND PHASE
5
4
1
1
DATA PHASE
4
0/1
7
0
6
1
3
0
2
0
1
0
0
0
7
d
6
d
5
d
3
d
2
d
1
d
0
FIFO Status 0
0/1
There is no address associated with reading the FIFO status 0 register.
2.7.3.4
FIFO Status 1 Register
The FIFO status 1 register returns two bits that report status and six unused bits.
7
6
5
4
3
2
1
0
FIFO Status 1
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
PRESENT
R/W
PRESENT
This bit identifies the VBI FIFO is read–only and is always set to 1.
This bit indicates the VBI FIFO is present and is always set to 1.
COMMAND PHASE
5
4
1
1
DATA PHASE
5
4
dc
dc
7
0
6
1
3
0
2
0
1
0
0
1
7
dc
6
dc
3
dc
2
dc
1
1
0
1
FIFO Status 1
There is no address associated with reading the FIFO status 1 register.
2.7.3.5
VBI FIFO
The VBI FIFO stores sliced VBI data. The data may be read from the FIFO at an average rate of one data
byte per three cycles (1 data cycle and 2 wait cycles) when the VIPCLK is at maximum speed.
COMMAND PHASE
5
4
1
1
DATA PHASE
5
4
D
D
7
0
6
1
3
0
2
1
1
0
0
0
7
D
6
D
3
D
2
D
1
D
0
D
FIFO VBI data read
There is no address associated with reading the VBI FIFO.
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