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參數(shù)資料
| 型號(hào)： | TVP5020TQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | NTSC/PAL VIDEO DECODER |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 41/87頁 |
| 文件大?。?/td> | 387K |
| 代理商： | TVP5020TQFP |
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2–27
VMI modes A and B are from the Video Electronics Standards Association (VESA) video module interface
(VMI) proposal version 1.4. Mode C is designed to conform to the interface requirements of the IBM
PowerPC 403GC. Table 2–8 summarizes the terminal functions of the VMI mode host interface.
Table 2–8. VMI Host Port Terminal Definitions
SIGNAL
VMI SIGNAL
NAME
TYPE
DESCRIPTION
VC3
CS
I
Chip select - modes A, B, and C
VC0
DTACK – mode A
READY – mode B
O (see below)
Data acknowledge – mode A
Data ready – modes B and C
VC1
R/W – mode A
WR – mode B
I
Read/write – modes A and C
Write strobe – mode B
VC2
DS – mode A
RD – mode B
I
Data strobe – mode A and C
Read strobe – mode B
A1:A0
HA[1:0]
I
Address bus from host
D7:D0
HD[7:0]
I/O
Input/output data bus from host
INTREQ
INTREQ is a nominally open drain terminal that signals interrupts to the host controller. The interrupt
configuration register at subaddress C2 can configure this terminal as a conventional CMOS I/O buffer
(non-open drain). Conflict is possible if INTREQ is connected to multiple devices and INTREQ is not
configured in the open drain mode.
INTREQ
O (nominal open drain)
Interrupt request
VC0 (DTACK/READY) is in the high impedance state when VC3 is not asserted.
2.9
Host Port – Mode A Timing
Host port mode A has a bus interface that accommodates the Motorola type of control signals. The diagram
below shows the timing of the mode A signals. The host initiates the cycle when VC2 transitions low. The
target responds by pulling VC0 low to indicate it is receiving the data or that the requested data is present
on the bus. The host completes its cycle by pulling VC2 high. Once the host completes its cycle, the target
pulls VC0 high. The host may change VC1, A[1:0], and Din[7:0] as soon as it receives VC0.
205 ns Max
85 ns Min
20 ns Min
Read Data
Write Data
VC2 (DS)
VC1 (R/W)
A (0–1)
D IN (0–7)
D OUT (0–7)
VC0 (DTACK)
Figure 2–26. VMI Host Port Mode A Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP5031 | NTSC/PAL VIDEO DECODER |
| TVP5031TQFP | NTSC/PAL VIDEO DECODER |
| TVP5031CPFP | Color Decoder Circuit |
| TVR4J | TOSHIBA Fast Recovery Diode Silicon Diffused Type High Speed Rectifier Applications (fast recovery) |
| TVR4N | TOSHIBA Fast Recovery Diode Silicon Diffused Type High Speed Rectifier Applications (fast recovery) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5021PFP | 功能描述:視頻 IC NTSC/PAL DIGITAL VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5021PFPG4 | 功能描述:視頻 IC NTSC/PAL DIGITAL VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5031 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
| TVP5031CPFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Color Decoder Circuit |
| TVP5031PFP | 功能描述:IC 9-BIT VIDEO DECODER 80-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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