參數(shù)資料
型號: TVP5020TQFP
廠商: Texas Instruments, Inc.
英文描述: NTSC/PAL VIDEO DECODER
中文描述: NTSC / PAL視頻解碼器
文件頁數(shù): 63/87頁
文件大?。?/td> 387K
代理商: TVP5020TQFP
2–49
2.15.19 Horizontal Sync (HSYN) Start
VIP address
116–117
VMI address
I2C address
16–17
16–17
Address
7
6
5
4
3
2
1
0
16
HSYN start for NTSC
17
HSYN start for PAL
HSYN start:
1 1 1 1 1 1 1 1 = –127
×
4 pixel clocks
1 1 1 1 1 1 1 0 = –126
×
4 pixel clocks
1 1 1 1 1 1 0 1 = –125
×
4 pixel clocks
1 0 0 0 0 0 0 0 = 0 pixel clocks (default)
0 1 1 1 1 1 1 1 = 1
×
4 pixel clocks
0 1 1 1 1 1 1 0 = 2
×
4 pixel clocks
0 0 0 0 0 0 0 0 = 128
×
4 pixel clocks
2.15.20 Vertical Blanking Start
VIP address
118
VMI address
I2C address
18
18
7
6
5
4
3
2
1
0
VBLK start
VBLK start:
0 1 1 1 1 1 1 1 = 127 lines after start of vertical blanking interval
0 0 0 0 0 0 0 1 = 1 line after start of vertical blanking interval
0 0 0 0 0 0 0 0 = Same time as start of vertical blanking interval (default)
0 1 1 1 1 1 1 1 = 1 line before start of vertical blanking interval
1 0 0 0 0 0 0 0 = 128 lines before start of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals as shown in
Figure 2–17
.
The setting in this register determines the timing of the GPCL signal when it is configured to
output vertical blank (see register 03). The setting in this register is also used to determine the duration of
the luma bypass function (see register 07).
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