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參數(shù)資料
| 型號(hào)： | TVP5020TQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | NTSC/PAL VIDEO DECODER |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 38/87頁 |
| 文件大?。?/td> | 387K |
| 代理商： | TVP5020TQFP |
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2–24
DC
Command
VC3
VC0
VC1
VC2
Wait
Address
Command
Slave Termination
Figure 2–25. Functional Timing Example of Slave Termination
VIP Configuration Register:
The TVP5020 supports VIP configuration registers that are accessible only in the VIP host mode.
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(from TVP5020)
7
0
6
1
5 4 3
1 0 0
2
0
1
0
0
0
7
A A A A A A A A D D D D D D D D
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VIP Config. Register read
General TVP5020 Registers:
The bulk of the TVP5020 register space consists of status and control registers that are available to the I
2
C,
VIP, and VMI host modes.
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(from TVP5020)
7
0
6
1
5 4 3
1 0 0
2
0
1
0
0
1
7
A A A A A A A A D D D D D D D D
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
General TVP register read
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(to TVP5020)
7
0
6
1
5 4 3
0 0 0
2
0
1
0
0
1
7
A A A A A A A A D D D D D D D D
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
General TVP register write
2.7.3.2
No-latency Read
No-latency read eliminates the extended wait states of normal read operations. No latency read consists
of two zero-wait state phases separated by an idle period during which the host may perform other
operations. The first phase identifies the register address to be read. This will be stored in an intermediate
data buffer. The current data in the intermediate data buffer is immediately read out. This information is to
be ignored because it is invalid data.
Following the completion of the first phase, the host must wait for at least 64
μ
s to ensure that the data
requested in the first phase is stored in the intermediate data buffer. The host initiates the second phase
of the read by reading the data from the intermediate data buffer.
No Latency Read Phase 1:
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(from TVP5020)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
No latency read
phase 1
0
1
1
0
0
0
1
0 A A A A A A A A
du
du
du
du
du
du
du
du
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP5031 | NTSC/PAL VIDEO DECODER |
| TVP5031TQFP | NTSC/PAL VIDEO DECODER |
| TVP5031CPFP | Color Decoder Circuit |
| TVR4J | TOSHIBA Fast Recovery Diode Silicon Diffused Type High Speed Rectifier Applications (fast recovery) |
| TVR4N | TOSHIBA Fast Recovery Diode Silicon Diffused Type High Speed Rectifier Applications (fast recovery) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5021PFP | 功能描述:視頻 IC NTSC/PAL DIGITAL VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5021PFPG4 | 功能描述:視頻 IC NTSC/PAL DIGITAL VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5031 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
| TVP5031CPFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Color Decoder Circuit |
| TVP5031PFP | 功能描述:IC 9-BIT VIDEO DECODER 80-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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