參數(shù)資料
型號(hào): TVP5031
廠商: Texas Instruments, Inc.
英文描述: NTSC/PAL VIDEO DECODER
中文描述: NTSC / PAL視頻解碼器
文件頁(yè)數(shù): 33/85頁(yè)
文件大小: 378K
代理商: TVP5031
2–17
Table 2–3 summarizes the terminal functions of the I
2
C-mode host interface.
Table 2–3. I
2
C Host Port Terminal Description
SIGNAL
TYPE
DESCRIPTION
VC3 (I2CA)
I
Slave address selection
VC0 (SCL)
I/O (open drain)
Input/output clock line
VC1 (SDA)
I/O (open drain)
Input/output data line
9
ACK
8
DATA
9
ACK
1-7
DATA
VC1(SDA)
P
Stop
I2C Data Transfer
8
DATA
9
ACK
1-7
DATA
8
RW
1-7
ADDRESS
S
Start Condition
VC0(SCL)
VC1(SDA)
VC0(SCL)
Figure 2–26. I
2
C Data Transfer Example
Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent on
the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the clock. The
high or low state of the data line can only change with the clock signal on the SCL line being low.
If multiple bytes are transferred during one read or write operation, the internal subaddress is automatically
incremented.
A high to low transition on the SDA line while the SCL is high indicates a start condition.
A low to high transition on the SDA line while the SCL is high indicates a stop condition.
Acknowledge (SDA Low)
Not-Acknowledge (SDA High)
Every byte placed on the SDA line must be 8-bits long. The number of bytes which can be transferred is unrestricted.
Each byte must be followed by an acknowledge bit. If the slave cannot receive another complete byte of data until
it has performed another function, it can hold the clock line (SCL) low to force the master into a wait state. Data transfer
then continues when the slave is ready for another byte of data and release the clock line (SCL).
Data transfer with acknowledge is obligatory. The acknowledge related clock pulse is generated by the master. The
master releases the SDA line high during the acknowledge clock pulse. The slave must pull down the SDA line during
the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse.
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