參數(shù)資料
型號(hào)： TVP5031
廠商： Texas Instruments, Inc.
英文描述： NTSC/PAL VIDEO DECODER
中文描述： NTSC / PAL視頻解碼器
文件頁(yè)數(shù)： 48/85頁(yè)
文件大?。?/td> 378K
代理商： TVP5031
2–32
Table 2–10. Data ID
DATA ID
EVENT IN SOURCE STREAM
DATA TYPE
50
Start of first, odd field
Dummy timing block
91
Sliced data of lines 1-23 of first field
VBI data
92
End of nominal VBI of first field, line 23
Dummy timing block
53
Sliced data of line 24 to end of first field
Full field teletext data
94
Start of second, even field
Dummy timing block
55
Sliced data of lines 1-23 of second field
VBI data
56
End of nominal VBI of second field, line 23
Dummy timing block
97
Sliced data of line 24 to end of second field
Full field teletext data
A dummy timing block will be inserted into the video stream during the horizontal blanking period following line 23
of each field. If teletext data is available from line 23 it will be inserted into the video stream prior to the dummy timing
block.
2.8
Raw Video Data Output
The TVP5031 can output raw A/D samples in the ITU-656 VBI video stream if desired in order to process VBI data
externally. The data occurs at the 2x pixel rate. The data is preceded by a preamble sequence of 00, FF, FF, 60. The
preamble sequence occurs immediately following the start of active video (SAV) sequence.
2.9
Reset and Initialization
Reset is initiated at power up or any time the RSTINB terminal is brought low. Table 2–11 describes the status of the
TVP5031s terminals during and immediately after reset. Following a power up reset, the host must download
microcode to the TVP5031s program memory for use by the internal microprocessor.
Table 2–11. Reset Sequence
SIGNAL NAMES
DURING RESET
RESET COMPLETED
Y[9:0], UV[9:0], HSYN,
VSYN, FID, PALI
Input
High-impedance if AVID is pulled down during reset.
Active output if AVID is pulled up during reset.
AVID
Input
High-impedance if AVID is pulled down during reset.
Active output if AVID is pulled up during reset.
SCLK, PCLK
High-impedance if PREF is pulled down during reset.
Active if PREF is pulled up during reset.
Active output
PREF
Input
Active output
GLCO
Input
Active output
VC0
High impedance
High impedance
D[7:0]
Input
High impedance
A[1:0] in PHI mode
Input
Input
RSTINB, SDA, SCL,
I2CA, OEB, GPCL
Input
Input
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