參數(shù)資料
型號(hào): TVP5031
廠(chǎng)商: Texas Instruments, Inc.
英文描述: NTSC/PAL VIDEO DECODER
中文描述: NTSC / PAL視頻解碼器
文件頁(yè)數(shù): 73/85頁(yè)
文件大?。?/td> 378K
代理商: TVP5031
2–57
2.11.47 Interrupt Status Register A
Address
C0h
7
6
5
4
3
2
1
0
Interrupt Status Register A (R/W)
TvpLOCK
State
TvpLOCK
Interrupt
Cycle
Complete
Bus Error
CC Odd
Field
CC Even
Field
Teletext
Threshold
Teletext
Data
Teletext Data
*0 = Teletext data buffer empty or we have not reached the video line number that equals
the interrupt line number register
1 = Teletext data buffer contains a complete transaction and the video line number =
interrupt line number register
Note this bit can be configured to occur whenever the video line number = interrupt line
number register regardless of the data.
*0 = Threshold not reached
1 = Teletext data in buffer has reached configurable threshold
*0 = Buffer empty
1 = Even field closed caption buffer contains data
*0 = Buffer empty
1 = Odd field closed caption buffer contains data
*0 = No bus error
1 = PHI interface detected an illegal access
*0 = Read or write cycle in progress
1 = Read or write cycle complete
*0 = A transition has not occurred on the tvpLOCK signal
1 = A transition has occurred on the tvpLOCK signal
Note, an interrupt will be generated on any transition of the lock signal.
*0 = TVP not locked to video
1 = TVP locked to video signal
Reflects the present state of the tvpLOCK.
Teletext Threshold
CC Even Field
CC Odd Field
Bus Error
Cycle Complete
tvpLOCK Interrupt
tvpLOCK State
The interrupt status register A is polled by the external processor to determine the interrupt source. After an interrupt
condition is set, it can be reset by writing to this register with a 1 in the appropriate bit(s).
2.11.48 Interrupt Enable Register A
Address
C1h
7
6
5
4
3
2
1
0
Interrupt Enable Register A (R/W)
tvpLOCK
State
tvpLOCK
Interrupt
Enable
Cycle
Complete
Enable
Bus Error
Enable
CC Odd
Field
Enable
CC Even
Field
Enable
Teletext
Threshold
Enable
Teletext
Data
Enable
The interrupt enable register A is used by the external processor to mask unnecessary interrupt sources for interrupt
A. Bits loaded with a 1 will allow the corresponding interrupt condition to generate an interrupt on the external terminal.
Conversely bits loaded with a 0 will mask the corresponding interrupt condition from generating an interrupt on the
external terminal. Note this register only affects the interrupt A on external terminal, it does not affect the bits in the
interrupt status register A. A given condition can set the appropriate bit in the status register and not cause an interrupt
on the external terminal. To determine if this device is driving the interrupt terminal, either perform a logical AND of
the interrupt status register B with the interrupt enable register B or check the state of the interrupt B bit in the interrupt
B active register.
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