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參數資料
| 型號： | TVP5031 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | NTSC/PAL VIDEO DECODER |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數： | 43/85頁 |
| 文件大?。?/td> | 378K |
| 代理商： | TVP5031 |
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2–27
2.6.5
Parallel Host Interface Register Map
The parallel host interface (PHI) module contains only four registers that are directly accessible to the host (see
Figure 2–30). The address register holds an indirect address for internal register access. When the host accesses
the data register the PHI module reads or writes the internal register selected by the indirect address register. Two
other registers are provided for direct access. The FIFO register provides direct access to the VBI FIFO. The other
direct access register is the status/Interrupt register. This register contains the state of the interrupt sources.
00
Address Register
A[1:0]
01
Data Register
10
FIFO
11
Status Register
Figure 2–30. PHI Address Register Map
Normally read or write operations require two accesses. To read the FIFO register, set A[1:0] to 2’b10 and perform
a read cycle. The FIFO read data will be placed on the D[7:0] bus. To read/write the status/interrupt register, set A[1:0]
to 2’b11 and perform the read/write cycle. The read/write data will be appropriately muxed to/from the external data
bus.
Indirect register read/write
All PHI accesses except for the VBI FIFO and the status/interrupt register require a two-step operation. To access
an indirect register the desired internal address must first be written to the address register of the PHI. This is done
by setting A[1:0] to 00 and performing a write cycle with D[7:0] = indirect register address. To write to an indirect
register, the second step consists of writing the desired data to PHI address 01. To read an indirect register, the second
step consists of reading the requested data from address 01.
Read Indirect Register
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
0
Register address
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read register data
0
1
Data from register
Write Indirect Register
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
0
Register address
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read register data
0
1
Data to register
Latency
PHI accesses to indirect addresses 00-8F require special consideration due to response latencies of up to 64
μ
s for
these addresses. Latency occurs between steps 1 and 2 for a read operation, and following step 2 for a write
operation. To avoid violating PHI cycle time requirements the host can poll the cycle complete bit in the PHI status
register following step 1 for a read or step 2 for a write. Alternatively, the cycle complete enable bit in the interrupt
enable register (indirect address C1) can be set to generate an interrupt for the host when an access has been
completed.
PHI accesses to indirect addresses 90-CF occur with minimal latency and interrupts will not be generated for the
completion of access cycles to these addresses.
相關PDF資料 |
PDF描述 |
|---|---|
| TVP5031TQFP | NTSC/PAL VIDEO DECODER |
| TVP5031CPFP | Color Decoder Circuit |
| TVR4J | TOSHIBA Fast Recovery Diode Silicon Diffused Type High Speed Rectifier Applications (fast recovery) |
| TVR4N | TOSHIBA Fast Recovery Diode Silicon Diffused Type High Speed Rectifier Applications (fast recovery) |
| TVU001 | 14 pin DIP, 5.0 Volt, HCMOS/TTL, Clock Oscillator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP5031CPFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Color Decoder Circuit |
| TVP5031PFP | 功能描述:IC 9-BIT VIDEO DECODER 80-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5031TQFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
| TVP5040 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL Digital Video Decoder With Macrovision Detection |
| TVP5040CPFP | 功能描述:IC NTSC/PAL VIDEO DECODER 80TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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