參數(shù)資料
型號: TVP5031
廠商: Texas Instruments, Inc.
英文描述: NTSC/PAL VIDEO DECODER
中文描述: NTSC / PAL視頻解碼器
文件頁數(shù): 74/85頁
文件大?。?/td> 378K
代理商: TVP5031
2–58
Address
C2h
7
6
5
4
3
2
1
0
Interrupt Configuration Register A (R/W)
Reserved
YUV Output Enable A
Interrupt A
Interrupt Polarity A
Interrupt Polarity
0 = Interrupt is active low
1 = Interrupt is active high
0 = Interrupt terminal is not active
1 = Interrupt terminal is active
Reflects state of Interrupt A on the external terminal. This bit is read only.
0 = YUV terminals are 3-state
1 = YUV terminals are active if other conditions are met
Interrupt A
YUV Output Enable A
The interrupt configuration register A is used to configure the polarity of the external in interrupt terminal. Note that
when the interrupt is configured for active low the terminal will be driven low when active and 3-state when inactive
(open-collector). Conversely, when the terminal is configured for active high it will be driven high for active and driven
low for inactive.
2.11.49 Parallel Host Interface Teletext FIFO
Address
10b
7
6
5
4
3
2
1
0
This read-only register is only accessible when the PHI interface is enabled. To access this register, use the direct
address of 10. Notice almost all the PHI registers are accessed through an indirect address scheme, by writing the
indirect address to address 00 and then write to or read from address 01. This register contains the same information
as the teletext FIFO register at indirect address B0 and is the recommended way of reading data from the teletext
FIFO due to its efficiency.
2.11.50 Parallel Host Interface Status/Interrupt A
Address
11b
7
6
5
4
3
2
1
0
This read-write register is only accessible when the PHI interface is enabled. To access this register, use the direct
address of 11. Notice almost all the PHI registers are accessed through an indirect address scheme, by writing the
indirect address to address 00 and then write to or read from address 01. This register contains the same information
as the interrupt status register A at indirect address C0. This is the recommended way of reading the interrupt/status
information due to its efficiency. After an interrupt condition is set, it can be reset by writing to this register with a 1
in the appropriate bit(s).
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