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參數(shù)資料
| 型號： | UPD17073 |
| 廠商： | NEC Corp. |
| 英文描述： | FILTER BAND PASS 5.8GHZ SMD |
| 中文描述： | 4位單芯片的數(shù)字調(diào)諧系統(tǒng)硬件單片機 |
| 文件頁數(shù)： | 27/226頁 |
| 文件大小： | 1250K |
| 代理商： | UPD17073 |
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27
μ
PD17072,17073
4.2 Configuration and Function of Data Memory
Figure 4-2 shows the configuration of the data memory.
As shown in this figure, the data memory is divided into three banks, and each bank consists of 128 nibbles with
7H row addresses and 0FH column addresses.
In terms of function, the data memory can be divided into six blocks each of which is described in the following
paragraphs 4.2.1 through 4.2.8.
The contents of the data memory can be operated, compared, judged, and transferred in 4-bit units by data memory
manipulation instructions.
Table 4-1 lists the data memory manipulation instructions.
4.2.1 System registers (SYSREG)
The system registers are allocated to addresses 74H through 7FH.
These registers are allocated independently of the bank and directly control the CPU. The same system registers
exist at addresses 74H through 7FH of each bank.
With the
μ
PD17073, only AR (address register: addresses 75H through 77H), BANK (bank register: address 79H),
and PSWORD (program status word: addresses 7EH and 7FH) can be manipulated.
For details, refer to
5. SYSTEM REGISTER (SYSREG)
.
4.2.2 Data buffer (DBF)
The data buffer is allocated to addresses 0CH through 0FH of BANK0.
The data buffer reads the constant data in the program memory (table reference), and transfers data with peripheral
hardware.
For details, refer to
9. DATA BUFFER (DBF)
.
4.2.3 General registers
With the
μ
PD17073, the general registers are fixed at row address 0 of BANK0, i.e., addresses 00H through 0FH,
and cannot be moved.
Operations and data transfer between the general registers and data memory can be executed with a single
instruction.
The general registers can be controlled by data memory manipulation instructions, like the other data memory
areas.
For details, refer to
6. GENERAL REGISTER (GR)
.
4.2.4 LCD segment registers
The LCD segment registers are allocated to addresses 41H through 4FH of BANK1 of the data memory, and are
used to set the display data of the LCD controller/driver.
For details, refer to
18. LCD CONTROLLER/DRIVER
.
4.2.5 Port registers
The port registers are allocated to addresses 70H through 73H of BANK0 and addresses 70H through 73H of
BANK1, and are used to set the output data of each general-purpose port and read the data of the input ports.
For details, refer to
10. GENERAL-PURPOSE PORT
.
4.2.6 Peripheral control registers
The peripheral control registers are allocated to addresses 50H through 6FH of BANK1 and are used to set the
conditions of the peripheral hardware (such as PLL, serial interface, A/D converter, IF counter, and timer).
For details, refer to
8. PERIPHERAL CONTROL REGISTER
.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| UPD17073GB | 制造商:NEC 制造商全稱:NEC 功能描述:4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM |
| UPD17073GB-XXX-1A7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| UPD17073GB-XXX-9EU | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| UPD1708AG-011 | 制造商:NEC 制造商全稱:NEC 功能描述:PLL FREQUENCY SYNTHESIZER AND CONTROLLER FOR FM/MW/LW TUNER |
| UPD1708AG-011-00 | 制造商:NEC 制造商全稱:NEC 功能描述:PLL FREQUENCY SYNTHESIZER AND CONTROLLER FOR FM/MW/LW TUNER |
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