CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT)
502
26.2.4 TDR (0x0C00 0050)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
W
W
W
W
W
W
W
W
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
R/W
W
W
W
W
W
W
W
W
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D15 to D8
Reserved
Write 0 when writing. 0 is returned after a read.
D7 to D0
TDR7 to 0
Transmit FIFO
[Function]
This register is used to store the address to which data is written for the transmit data store FIFO.
Up to 64- or 32-byte data (determined by bit 3 of FSR) is stored to the transmit data store FIFO.
Transmit data FIFO is used as follows.
(1) Write
Data is written to the transmit data store FIFO while the IrDA is operating.
When a write operation is completed, the write pointer of the transmit data store FIFO is incremented. However,
if data is written when this write pointer is full, it is not incremented.
After the data of frame size is written to the TXFL register in a status other than the transmit busy status (start
enable), if the data written to this register reaches frame size, data transfer starts even if the number of write to
this register is short of the threshold.
This is Start 1.
After that, data is always transferred if it reaches frame size, even if it is short of the threshold. This is Start 2.
(2) Read
After frame transfer is completed, the sequencer reads the transmit data during the data transfer sequence, and
the read pointer is incremented.
If read is done while the transmit FIFO is empty, a transmit underrun error occurs. This stops the current frame
transmission and then starts the abort frame transmission. The following frames scheduled to be transmitted
next are not transferred.