CHAPTER 28 V
R
4102 COPROCESSOR 0 HAZARDS
680
(8)
CACHE Index Store Tag
Source:
The confirmation of registers containing information necessary for executing this instruction.
(9)
Coprocessor Usable Test
Source:
The confirmation of modes set by the bits of the CP0 registers in the “Source” column.
Examples 1.
When accessing the CP0 registers in User mode after the content of the CU0 bit of the Status
register is modified, or when executing an instruction such as TLB instructions, CACHE
instructions, or branch instructions which use the resource of the CP0.
When accessing the CP0 registers in the operating mode set in the Status register after the
KSU, EXL, and ERL bits of the Status register are modified.
2.
(10) Instruction Fetch
Source:
The confirmation of the operating mode and TLB necessary for instruction fetch.
Examples 1.
When changing the operating mode from User to Kernel and fetching instructions after the
KSU, EXL, and ERL bits of the Status register are modified.
When fetching instructions using the modified TLB entry after TLB modification.
2.
(11) Instruction Fetch Exception
Destination: The completion of writing to registers containing information related to the exception when an
exception occurs on instruction fetch.
(12) Interrupts
Source:
The confirmation of registers judging the condition of occurrence of interrupt when an interrupt
factor is detected.
(13) Loads/Sores
Source:
The confirmation of the operating mode related to the address generation of Load/Store
instructions, TLB entries, the cache mode set in the K0 bit of the Config register, and the registers
setting the condition of occurrence of a Watch exception.
Example
When Loads/Stores are executed in the kernel field after changing the mode from User to Kernel.
(14) Load/Store Exception
Destination: The completion of writing to registers containing information related to the exception when an
exception occurs on load or store operation.
(15) TLB Shutdown
Destination: The completion of writing to the TS bit of the Status register when a TLB shutdown occurs.