參數(shù)資料
型號： UPD754244GS-XXX-GJG
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20
封裝： 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20
文件頁數(shù)： 26/90頁
文件大小： 602K
代理商： UPD754244GS-XXX-GJG
PD754144,
754244
30
Data
Sheet
U10040EJ2V1DS
Figure 8-1. Interrupt Control Circuit Block Diagram
Notes 1.
Noise eliminator (Standby release is disable when noise eliminator is selected.)
2.
The INT2 pin is not provided. Interrupt request flag (IRQ2) is set at the KRn pin falling edge when IM20 = 1 and IM21 = 0.
Internal bus
Interrupt enable flag (IE
×××)
24
IM2
IM0
Note1
Edge
detector
INT0/P61
INTBT
INTT0
INTT1
INTT2
INTEE
IRQBT
IRQ0
IRQT0
IRQT1
IRQT2
IRQEE
IRQ2
KR4/P70
KR7/P73
Falling edge
detectorNote2
Key return reset circuit
IM2
IME
IPS
IST1
IST0
Decoder
VRQn
Priority control
ciricuit
Standby release
signal
Selector
Vector table
address
generator
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