參數(shù)資料
型號： UPD754244GS-XXX-GJG
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20
封裝： 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20
文件頁數(shù)： 7/90頁
文件大?。?/td> 602K
代理商： UPD754244GS-XXX-GJG
PD754144, 754244
13
Data Sheet U10040EJ2V1DS
4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE
4.1 Difference between Mk I and Mk II Modes
The
PD754244 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The
mode can be switched by the bit 3 of the Stack Bank Select register (SBS).
Mk I mode:
Instructions are compatible with the 75X series. Can be used in the 75XL CPU with a ROM
capacity of up to 16 Kbytes.
Mk II mode:
Incompatible with 75X series. Can be used in all the 75XL CPU’s including those products
whose ROM capacity is more than 16 Kbytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I Mode
Mk II Mode
Number of stack bytes
2 bytes
3 bytes
for subroutine instructions
BRA !addr1 instruction
Not available
Available
CALLA !addr1 instruction
CALL !addr instruction
3 machine cycles
4 machine cycles
CALLF !faddr instruction
2 machine cycles
3 machine cycles
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.
Therefore, this mode is effective for enhancing software compatibility with products that
have a program area of more than 16 Kbytes.
With regard to the number of stack bytes during execution of subroutine call instructions,
the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II
mode is selected.
However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle
becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use
efficiency and processing performance than on software compatibility, the Mk I mode
should be used.
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