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參數(shù)資料
| 型號： | UPD754244GS-XXX-GJG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 27/90頁 |
| 文件大?。?/td> | 602K |
| 代理商： | UPD754244GS-XXX-GJG |
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PD754144, 754244
31
Data Sheet U10040EJ2V1DS
9. STANDBY FUNCTION
In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the
PD754244.
Table 9-1. Operation Status in Standby Mode
Item
Mode
STOP Mode
HALT Mode
Set instruction
STOP instruction
HALT instruction
Operation
Clock generator
Operation stops.
Only the CPU clock
Φ halts (oscillation
status
continues).
Basic interval timer/
Operation stops.
Operable
watchdog timer
BT mode: The IRQBT is set in the basic
time interval.
WT mode: Reset is generated by the
BT overflow.
Timer
Operation stops.
Operable.
External interrupt
INT0 is not operable.Note
INT2 is operable during KRn falling period only.
CPU
The operation stops.
Release signal
Reset signal
Reset signal
Interrupt request signal sent from
interrupt enabled peripheral hardware
System reset signal (key return reset)
generated by KRn falling edge when the
KRREN pin = 1
Note
Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode
register (IM0).
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