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參數(shù)資料
| 型號： | UPD754244GS-XXX-GJG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 30/90頁 |
| 文件大?。?/td> | 602K |
| 代理商： | UPD754244GS-XXX-GJG |
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PD754144, 754244
34
Data Sheet U10040EJ2V1DS
Table 10-1. Hardware Status After Reset (1/3)
Hardware
RESET signal generation
in the standby mode
in operation
Program counter (PC)
Sets the low-order 4 bits of
program memory’s address
0000H to the PC11-PC8 and the
contents of address 0001H to
the PC7-PC0.
PSW
Carry flag (CY)
Held
Undefined
Skip flag (SK0 to SK2)
0
Interrupt status flag (IST0, IST1)
0
Bank enable flag (MBE, RBE)
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Stack pointer (SP)
Undefined
Stack bank select register (SBS)
1000B
Data memory (RAM)
Held
Undefined
Data memory (EEPROM)
HeldNote 1
HeldNote 2
EEPROM write control register (EWC)
0
General-purpose register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
Basic interval
Counter (BT)
Undefined
timer/watchdog
Mode register (BTM)
0
timer
Watchdog timer enable flag (WDTM)
00
Timer counter
Counter (T0)
0
(channel 0)
Modulo register (TMOD0)
FFH
Mode register (TM0)
0
TOE0, TOUT F/F
0, 0
Timer counter
Counter (T1)
0
(channel 1)
Modulo register (TMOD1)
FFH
Mode register (TM1)
0
TOE1, TOUT F/F
0, 0
Timer counter
Counter (T2)
0
(channel 2)
Modulo register (TMOD2)
FFH
High-level period setting modulo
FFH
register (TMOD2H)
Mode register (TM2)
0
TOE2, TOUT F/F
0, 0
REMC, NRZ, NRZB
0, 0, 0
Notes 1.
Undefined if STOP mode is entered during an EEPROM write operation. Also undefined if HALT mode
is entered during a write operation and a RESET signal is input during a write operation.
2.
If a RESET signal is input during an EEPROM write operation, the data at that address is undefined.
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