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參數(shù)資料
| 型號： | UPD754244GS-XXX-GJG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 50/90頁 |
| 文件大?。?/td> | 602K |
| 代理商： | UPD754244GS-XXX-GJG |
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PD754144, 754244
52
Data Sheet U10040EJ2V1DS
PD754144
AC Characteristics (TA = –40 to +85
°C, VDD = 1.8 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle time Note1
tCY
2.0
4.0
128
s
(Minimum instruction execution
time = 1 machine cycle)
RC oscillation frequency
fCC
R = 22 k
,
VDD = 3.6 to 6.0 V
0.9
1.0 Note 2
1.2
MHz
C = 22 pF
VDD = 2.2 to 3.6 V
0.75
1.0 Note 2
1.15
MHz
VDD = 1.8 to 3.6 V
0.5
1.0 Note 2
1.15
MHz
VDD = 1.8 to 6.0 V
0.5
1.0 Note 2
1.2
MHz
R = 5.1 k
,
VDD = 3.6 to 6.0 V
0.91
1.0 Note 2
1.1
MHz
C = 120 pF
VDD = 2.2 to 3.6 V
0.76
1.0 Note 2
1.05
MHz
VDD = 1.8 to 3.6 V
0.51
1.0 Note 2
1.05
MHz
VDD = 1.8 to 6.0 V
0.51
1.0 Note 2
1.1
MHz
Interrupt input high- and
tINTH, tINTL
INT0
IM02 = 0
Note 3
s
low-level width
IM02 = 1
10
s
KR4 to KR7
10
s
RESET low-level width
tRSL
10
s
Notes 1.
The CPU clock (
Φ) cycle time (minimum
instruction execution time) is determined
by the time constants of the connected
resistor (R) and capacitor (d) and the pro-
cessor clock control register (PCC). The
figure on the right shows the cycle time tCY
characteristics against the supply voltage
VDD when the system clock is used.
2.
This is the typical value when VDD = 3.6 V.
3.
2tCY or 128/fCC depending on the setting of
the interrupt mode register (IM0).
0.5
0
Supply voltage VDD (V)
12
3456
1.8
1
2
3
4
5
6
128
(During system clock operation)
tCY vs. VDD
Operation guranteed range
Cycle
time
t
CY
(
s)
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