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參數(shù)資料
| 型號(hào)： | V54C316802VB |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | High Performance 3.3 Volt 2M X 8 Synchronous DRAM(3.3V高性能2Mx8同步動(dòng)態(tài)RAM) |
| 中文描述： | 高性能3.3伏200萬× 8同步DRAM（3.3V的高性能2Mx8同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 2/60頁 |
| 文件大小： | 586K |
| 代理商： | V54C316802VB |
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V54C316802VB Rev. 1.0 February 1999
MOSEL V ITELIC
V54C316802VB
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write with Auto-Precharge
8. Burst Termination
8.1 Termination of a full Page Burst Write Operation
8.2 Termination of a Full Page Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Clock Suspension (using CKE)
12.1 Clock Suspension During Burst Read CAS Latency = 1
12. 2 Clock Suspension During Burst Read CAS Latency = 2
12. 3 Clock Suspension During Burst Read CAS Latency = 3
12. 4 Clock Suspension During Burst Write CAS Latency = 1
12. 5 Clock Suspension During Burst Write CAS Latency = 2
12. 6 Clock Suspension During Burst Write CAS Latency = 3
13. Power Down Mode and Clock Suspend
14. Auto Refresh (CBR)
15. Self Refresh (Entry and Exit)
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