參數(shù)資料
型號(hào): V54C316802VB
廠商: Mosel Vitelic, Corp.
英文描述: High Performance 3.3 Volt 2M X 8 Synchronous DRAM(3.3V高性能2Mx8同步動(dòng)態(tài)RAM)
中文描述: 高性能3.3伏200萬(wàn)× 8同步DRAM(3.3V的高性能2Mx8同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 5/60頁(yè)
文件大?。?/td> 586K
代理商: V54C316802VB
16
V54C316802VB Rev. 1.0 February 1999
MOSEL V ITELIC
V54C316802VB
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 1, 2, 3)
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
t
CK1,
I/O’s
CAS latency = 1
t
CK2,
I/O’s
CAS latency = 2
t
CK3,
I/O’s
CAS latency = 3
NOP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DQM
DOUT A0
DIN B0
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
I/O’s
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
t
DQZ
t
DQW
: “H” or “L”
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