參數(shù)資料
型號(hào): V54C316802VB
廠商: Mosel Vitelic, Corp.
英文描述: High Performance 3.3 Volt 2M X 8 Synchronous DRAM(3.3V高性能2Mx8同步動(dòng)態(tài)RAM)
中文描述: 高性能3.3伏200萬(wàn)× 8同步DRAM(3.3V的高性能2Mx8同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 4/60頁(yè)
文件大小: 586K
代理商: V54C316802VB
15
V54C316802VB Rev. 1.0 February 1999
MOSEL V ITELIC
V54C316802VB
1. Bank Activate Command Cycle
(CAS latency = 3)
2. Burst Read Operation
(Burst Length = 4, CAS latency = 1, 2, 3)
T0
T1
ADDRESS
CLK
T0
T
T1
T
T
T
T
COMMAND
NOP
NOP
NOP
Bank A
Row Addr.
Bank A
Activate
Write A
Precharge
Bank A
Col. Addr.
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
Bank B
Activate
Bank A
Row Addr.
Bank A
Activate
t
RCD
: “H” or “L”
t
RC
t
RRD
Bank B
Row Addr.
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0
CAS latency = 1
t
CK1,
I/O’s
t
CK2,
I/O’s
CAS latency = 2
t
CK3,
I/O’s
CAS latency = 3
DOUT A1
DOUT A2
DOUT A3
NOP
CLK
T2
T3
T4
T5
T6
T7
T8
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
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