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參數(shù)資料
| 型號： | V54C316802VB |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | High Performance 3.3 Volt 2M X 8 Synchronous DRAM(3.3V高性能2Mx8同步動態(tài)RAM) |
| 中文描述： | 高性能3.3伏200萬× 8同步DRAM（3.3V的高性能2Mx8同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 60/60頁 |
| 文件大?。?/td> | 586K |
| 代理商： | V54C316802VB |
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12
V54C316802VB Rev. 1.0 March 1998
MOSEL V ITELIC
V54C316802VB
Notes:
1.
2.
For proper power-up see the operation section of this data sheet.
AC timing tests for LV-TTL versions have V
= 0.8V and V
= 2.0V with the timing referenced to the 1.4 V crossover point. The
transition time is measured between V
and V
. All AC measurements assume t
=1ns with the AC output load circuit shown in fig.
1. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of
1V / ns edge rate between 0.8V and 2.0V..
3.
4.
5.
If clock rising time is longer than 1 ns, a time (t
/2 - 0.5) ns has to be added to this parameter.
If tT is longer than 1 ns, a time (t
-1) ns has to be added to this parameter.
These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit
is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered.
1.4V
1.4V
tSETUP
tHOLD
tAC
tAC
tLZ
tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
2.0V
0.8V
t
T
tCH
50 pF
Measurement conditions for
tac and toh
Fig. 1
I/O
tCL
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