
VLSI
Solution
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VS1003 PRELIMINARY
VS1003
7. SPI BUSES
7.3
Data Request Pin DREQ
The DREQ pin/signal is used to signal if VS1003’s FIFO is capable of receiving data. If DREQ is high,
VS1003 can take at least 32 bytes of SDI data or one SCI command. When these criteria are not met,
DREQ is turned low, and the sender should stop transferring new data.
Because of the 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time without
checking the status of DREQ, making controlling VS1003 easier for low-speed microcontrollers.
Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should
only be used to decide whether to send more bytes. It should not abort a transmission that has already
started.
Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1003 DREQ is also used
to tell the status of SCI.
7.4
Serial Protocol for Serial Data Interface (SDI)
7.4.1
General
The serial data interface operates in slave mode so DCLK signal must be generated by an external circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.6).
VS1003 assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or LSb
first, depending of contents of SCI MODE (Chapter 8.6.1).
The firmware is able to accept the maximum bitrate the SDI supports.
7.4.2
SDI in VS1002 Native Modes (New Mode)
InVS1002nativemodes(SM NEWMODEis1), bytesynchronizationisachievedbyXDCS.Thestateof
XDCS may not change while a data byte transfer is in progress. To always maintain data synchronization
even if there may be glitches in the boards using VS1003, it is recommended to turn XDCS every now
and then, for instance once after every flash data block or a few kilobytes, just to keep sure the host and
VS1003 are in sync.
If SM SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.
For new designs, using VS1002 native modes are recommended.
Version 0.92,
2005-06-07
17