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參數(shù)資料
| 型號： | VS1003 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | MP3 / WMA AUDIO CODEC |
| 中文描述： | MP3播放/ WMA音頻編解碼器 |
| 文件頁數(shù)： | 48/57頁 |
| 文件大小： | 456K |
| 代理商： | VS1003 |
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VLSI
Solution
y
VS1003 PRELIMINARY
VS1003
10. VS1003 REGISTERS
10.11.3
Data UARTx DATA
A read from UARTx DATA returns the received byte in bits 7:0, bits 15:8 are returned as ’0’. If there is
no more data to be read, the receiver data register full indicator will be cleared.
A receive interrupt will be generated when a byte is moved from the receiver shift register to the receiver
data register.
A write to UARTx DATA sets a byte for transmission. The data is taken from bits 7:0, other bits in the
written value are ignored. If the transmitter is idle, the byte is immediately moved to the transmitter shift
register, a transmit interrupt request is generated, and transmission is started. If the transmitter is busy,
the UART ST TXFULL will be set and the byte remains in the transmitter data register until the previous
byte has been sent and transmission can proceed.
10.11.4
Data High UARTx DATAH
The same as UARTx DATA, except that bits 15:8 are used.
10.11.5
Divider UARTx DIV
UARTx DIV Bits
Description
Divider 1 (0..255)
Divider 2 (6..255)
Name
UART DIV D1
UART DIV D2
Bits
15:8
7:0
The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending on the
master clock frequency to get the correct bit speed. The second divider (
D
2
) must be from 6 to 255.
The communication speed
f
=
TX/RX speed in bps.
f
m
(
D
1
+1)
×
(
D
2
)
, where
f
m
is the master clock frequency, and
f
is the
Divider values for common communication speeds at 26 MHz master clock:
Example UART Speeds,
f
m
= 26
MHz
Comm. Speed [bps]
UART DIV D1
4800
9600
14400
19200
28800
38400
57600
115200
UART DIV D2
85
42
42
51
42
25
63
63
42
26
21
26
226
226
1
0
Version 0.92,
2005-06-07
48
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