- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359422 > VS1003 (Electronic Theatre Controls, Inc.) MP3 / WMA AUDIO CODEC PDF資料下載
參數(shù)資料
| 型號(hào)： | VS1003 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | MP3 / WMA AUDIO CODEC |
| 中文描述： | MP3播放/ WMA音頻編解碼器 |
| 文件頁數(shù)： | 49/57頁 |
| 文件大?。?/td> | 456K |
| 代理商： | VS1003 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當(dāng)前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
VLSI
Solution
y
VS1003 PRELIMINARY
VS1003
10. VS1003 REGISTERS
10.11.6
Interrupts and Operation
Transmitter operates as follows: After an 8-bit word is written to the transmit data register it will be
transmitted instantly if the transmitter is not busy transmitting the previous byte. When the transmission
begins a TX INTR interrupt will be sent. Status bit [1] informs the transmitter data register empty (or
full state) and bit [0] informs the transmitter (shift register) empty state. A new word must not be written
to transmitter data register if it is not empty (bit [1] = ’0’). The transmitter data register will be empty
as soon as it is shifted to transmitter and the transmission is begun. It is safe to write a new word to
transmitter data register every time a transmit interrupt is generated.
Receiver operates as follows: It samples the RX signal line and if it detects a high to low transition, a
start bit is found. After this it samples each 8 bit at the middle of the bit time (using a constant timer),
and fills the receiver (shift register) LSB first. Finally if a stop bit (logic high) is detected the data in
the receiver is moved to the reveive data register and the RX INTR interrupt is sent and a status bit[2]
(receive data register full) is set, and status bit[2] old state is copied to bit[3] (receive data overrun). After
that the receiver returns to idle state to wait for a new start bit. Status bit[2] is zeroed when the receiver
data register is read.
RS232 communication speed is set using two clock dividers. The base clock is the processor master
clock. Bits 15-8 in these registers are for first divider and bits 7-0 for second divider. RX sample
frequency is the clock frequency that is input for the second divider.
Version 0.92,
2005-06-07
49
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VS100 | Interface IC |
| VS100AE | CAMERA MONOCHROME |
| VS1024 | AREA CCD IMAGE ARRAY |
| VS10P05 | Direct ProTek Replacement:VS10P05 |
| VS10P05C | Direct ProTek Replacement:VS10P05C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VS1003-BB | 制造商:Distributed By MCM 功能描述:VS1003 MP3/WMA BREAKOUT BOARD |
| VS1003B-L | 制造商:CONSONANCE 制造商全稱:CONSONANCE 功能描述:芬蘭VLSI廠家生產(chǎn)的音頻編解碼芯片 |
| VS100-48 | 制造商:TDK-Lambda Corporation 功能描述:105.6W AC To DC Switching Power Supply - 85-132V/110-175V in - 48V 2.2A out |
| VS1005 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:此產(chǎn)品是芬蘭VLSI剛剛研發(fā)成功的音頻編解碼芯片樣品 |
| VS100AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CAMERA MONOCHROME |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。