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參數(shù)資料
| 型號(hào)： | VS1003 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | MP3 / WMA AUDIO CODEC |
| 中文描述： | MP3播放/ WMA音頻編解碼器 |
| 文件頁數(shù)： | 19/57頁 |
| 文件大?。?/td> | 456K |
| 代理商： | VS1003 |
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VLSI
Solution
y
VS1003 PRELIMINARY
VS1003
7. SPI BUSES
7.5.2
SCI Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
30
31
14
15
16
17
0
0
0
0
0
0
1
1
0
0
0
0
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
1
0
X
instruction (read)
address
data out
XCS
SCK
SI
SO
don’t care
don’t care
DREQ
execution
Figure 6: SCI Word Read
VS1003 registers are read from using the following sequence, as shown in Figure 6. First, XCS line is
pulled low to select the device. Then the READ opcode (0x3) is transmitted via the SI line followed by
an 8-bit word address. After the address has been read in, any further data on SI is ignored by the chip.
The 16-bit data corresponding to the received address will be shifted out onto the SO line.
XCS should be driven high after data has been shifted out.
DREQ is driven low for a short while when in a read operation by the chip. This is a very short time and
doesn’t require special user attention.
7.5.3
SCI Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
30
31
14
15
16
17
0
0
0
0
0
0
1
0
0
0
0
3
2
1
0
1
0
X
address
XCS
SCK
SI
15
14
data out
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SO
0
0
0
0
X
0
instruction (write)
DREQ
execution
Figure 7: SCI Word Write
VS1003 registers are written from using the following sequence, as shown in Figure 7. First, XCS line
is pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followed
by an 8-bit word address.
Version 0.92,
2005-06-07
19
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相關(guān)代理商/技術(shù)參數(shù) |
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| VS1003-BB | 制造商:Distributed By MCM 功能描述:VS1003 MP3/WMA BREAKOUT BOARD |
| VS1003B-L | 制造商:CONSONANCE 制造商全稱:CONSONANCE 功能描述:芬蘭VLSI廠家生產(chǎn)的音頻編解碼芯片 |
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| VS1005 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:此產(chǎn)品是芬蘭VLSI剛剛研發(fā)成功的音頻編解碼芯片樣品 |
| VS100AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CAMERA MONOCHROME |
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