- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359422 > VS1003 (Electronic Theatre Controls, Inc.) MP3 / WMA AUDIO CODEC PDF資料下載
參數(shù)資料
| 型號(hào)： | VS1003 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | MP3 / WMA AUDIO CODEC |
| 中文描述： | MP3播放/ WMA音頻編解碼器 |
| 文件頁數(shù)： | 50/57頁 |
| 文件大?。?/td> | 456K |
| 代理商： | VS1003 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
VLSI
Solution
y
VS1003 PRELIMINARY
VS1003
10. VS1003 REGISTERS
10.12
Timers
v1.0 2002-04-23
There are two 32-bit timers that can be initialized and enabled independently of each other. If enabled,
a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle.
When the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start value
register, and continues downcounting. A timer stays in that loop as long as it is enabled.
A timer has a 32-bit timer register for down counting and a 32-bit TIMER1 LH register for holding the
timer start value written by the processor. Timers have also a 2-bit TIMER ENA register. Each timer is
enabled (1) or disabled (0) by a corresponding bit of the enable register.
10.12.1
Registers
Timer registers, prefix TIMER
Reset
Abbrev
0
CONFIG[7:0]
0
ENABLE[1:0]
0
T0L
0
T0H
0
T0CNTL
0
T0CNTH
0
T1L
0
T1H
0
T1CNTL
0
T1CNTH
Reg
Type
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Description
Timer configuration
Timer enable
Timer0 startvalue - LSBs
Timer0 startvalue - MSBs
Timer0 counter - LSBs
Timer0 counter - MSBs
Timer1 startvalue - LSBs
Timer1 startvalue - MSBs
Timer1 counter - LSBs
Timer1 counter - MSBs
0xC030
0xC031
0xC034
0xC035
0xC036
0xC037
0xC038
0xC039
0xC03A
0xC03B
10.12.2
Configuration TIMER CONFIG
TIMER CONFIG Bits
Bits
Description
7:0
Master clock divider
Name
TIMER CF CLKDIV
TIMER CF CLKDIV is the master clock divider for all timer clocks. The generated internal clock
frequency
f
i
=
With a 12 MHz master clock, TIMER CF DIV=3 divides the master clock by 4, and the output/sampling
clock would thus be
f
i
=
12
MHz
3+1
= 3
MHz
.
f
m
, where
f
m
is the master clock frequency and
c
is TIMER CF CLKDIV. Example:
Version 0.92,
2005-06-07
50
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VS100 | Interface IC |
| VS100AE | CAMERA MONOCHROME |
| VS1024 | AREA CCD IMAGE ARRAY |
| VS10P05 | Direct ProTek Replacement:VS10P05 |
| VS10P05C | Direct ProTek Replacement:VS10P05C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VS1003-BB | 制造商:Distributed By MCM 功能描述:VS1003 MP3/WMA BREAKOUT BOARD |
| VS1003B-L | 制造商:CONSONANCE 制造商全稱:CONSONANCE 功能描述:芬蘭VLSI廠家生產(chǎn)的音頻編解碼芯片 |
| VS100-48 | 制造商:TDK-Lambda Corporation 功能描述:105.6W AC To DC Switching Power Supply - 85-132V/110-175V in - 48V 2.2A out |
| VS1005 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:此產(chǎn)品是芬蘭VLSI剛剛研發(fā)成功的音頻編解碼芯片樣品 |
| VS100AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CAMERA MONOCHROME |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。