
VLSI
Solution
y
VS1003 PRELIMINARY
VS1003
8. FUNCTIONAL DESCRIPTION
8.6.4
SCI CLOCKF (RW)
The operation of SCI CLOCKF is different in VS1003 than in VS10x1 and VS1002.
SCI CLOCKF bits
Bits
Description
15:13
Clock multiplier
12:11
Allowed multiplier addition
10: 0
Clock frequency
Name
SC MULT
SC ADD
SC FREQ
SC MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI.
The values are as follows:
SC MULT
0
1
2
3
4
5
6
7
MASK
0x0000
0x2000
0x4000
0x6000
0x8000
0xa000
0xc000
0xe000
CLKI
XTALI
XTALI
×
1
.
5
XTALI
×
2
.
0
XTALI
×
2
.
5
XTALI
×
3
.
0
XTALI
×
3
.
5
XTALI
×
4
.
0
XTALI
×
4
.
5
SC ADDtells, howmuchthedecoderfirmwareisallowedtoaddtothemultiplierspecifiedbySC MULT
if more cycles are temporarily needed to decode a WMA stream. The values are:
SC ADD
0
1
2
3
MASK
0x0000
0x0800
0x1000
0x1800
Multiplier addition
No modification is allowed
0.5
×
1.0
×
1.5
×
SC FREQ is used to tell if the input clock XTALI is running at something else than 12.288 MHz. XTALI
is set in 4 kHz steps. The formula for calculating the correct value for this register is
XTALI
8000000
(XTALI is in Hz).
4000
Note: The default value 0 is assumed to mean XTALI=12.288 MHz.
Note: because maximum sample rate is
XTALI
MHz.
256
, all sample rates are not available if XTALI
<
12
.
288
Note: Automatic clock change can only happen when decoding WMA files. Automatic clock change
is done one
0
.
5
at a time. This does not cause a drop to
1
.
0
clock and you can use the same SCI
and SDI clock throughout the WMA file. When decoding ends the default multiplier is restored and can
cause
1
.
0
×
clock to be used momentarily.
Example: If SCI CLOCKF is 0x9BE8, SC MULT = 4, SC ADD = 3 and SC FREQ = 0x3E8 = 1000.
ThismeansthatXTALI=
1000
4000+8000000
=12MHz. Theclockmultiplierissetto
3
.
0
XTALI
=
36
MHz, and the maximum allowed multiplier that the firmware may automatically choose to use is
(3
.
0 + 1
.
5)
×
XTALI
= 54
MHz.
Version 0.92,
2005-06-07
32