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參數(shù)資料
| 型號： | VS1003 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | MP3 / WMA AUDIO CODEC |
| 中文描述： | MP3播放/ WMA音頻編解碼器 |
| 文件頁數(shù)： | 28/57頁 |
| 文件大小： | 456K |
| 代理商： | VS1003 |
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VLSI
Solution
y
VS1003 PRELIMINARY
VS1003
8. FUNCTIONAL DESCRIPTION
8.5
Serial Control Interface (SCI)
The serial control interface is compatible with the SPI bus specification. Data transfers are always 16
bits. VS1003 is controlled by writing and reading the registers of the interface.
The main controls of the control interface are:
control of the operation mode, clock, and builtin effects
access to status information and header data
access to encoded digital data
uploading user programs
8.6
SCI Registers
SCI registers, prefix SCI
Time
1
Abbrev[bits]
70 CLKI
4
MODE
40 CLKI
STATUS
2100 CLKI
BASS
11000 XTALI
5
CLOCKF
40 CLKI
DECODE TIME
3200 CLKI
AUDATA
80 CLKI
WRAM
80 CLKI
WRAMADDR
-
HDAT0
-
HDAT1
3200 CLKI
2
AIADDR
2100 CLKI
VOL
50 CLKI
2
AICTRL0
50 CLKI
2
AICTRL1
50 CLKI
2
AICTRL2
50 CLKI
2
AICTRL3
Reg
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Type
rw
rw
rw
rw
rw
rw
rw
rw
r
r
rw
rw
rw
rw
rw
rw
Reset
0x800
0x3C
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Mode control
Status of VS1003
Built-in bass/treble enhancer
Clock freq + multiplier
Decode time in seconds
Misc. audio data
RAM write/read
Base address for RAM write/read
Stream header data 0
Stream header data 1
Start address of application
Volume control
Application control register 0
Application control register 1
Application control register 2
Application control register 3
1
This is the worst-case time that DREQ stays low after writing to this register. The user may choose to
skip the DREQ check for those register writes that take less than 100 clock cycles to execute.
2
In addition, the cycles spent in the user application routine must be counted.
3
Firmware changes the value of this register immediately to 0x38, and in less than 100 ms to 0x30.
4
When mode register write specifies a software reset the worst-case time is 16600 XTALI cycles.
5
Writing to this register may force internal clock to run at
1
.
0
XTALI for a while. Thus it is not a
good idea to send SCI or SDI bits while this register update is in progress.
Note that if DREQ is low when an SCI write is done, DREQ also stays low after SCI write processing.
Version 0.92,
2005-06-07
28
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