參數(shù)資料
型號(hào)： VT6305
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： PCI 1394 Host Controller
中文描述： 1394主控制器的PCI
文件頁(yè)數(shù)： 10/35頁(yè)
文件大?。?/td> 220K
代理商： VT6305
Revision 0.2
March 10, 2000
-5-
Pinouts
Technologies, Inc.
WeConnect
Pin Descriptions
Table 1. VT6305 Pin Descriptions
PCI Bus Interface
Signal Name
Pin No.
I/O
Signal Description
AD[31:0]
1, 2, 4, 5, 7-10,
13, 15, 17-22, 36,
39, 41-44, 46, 47,
49-51, 53, 55-58
11, 24, 35, 48
IO
Address / Data Bus.
The standard PCI address and data lines. The address is
driven with FRAME# assertion and data is driven or received in following cycles.
CBE[3:0]#
IO
Command / Byte Enable.
The command is driven with FRAME# assertion. Byte
enables corresponding to supplied or requested data are driven on following clocks.
Frame.
Assertion indicates the address phase of a PCI transfer. Negation indicates
that one more data transfer is desired by the cycle initiator.
Device Select.
As an output, this signal is asserted to claim PCI transactions
through positive or subtractive decoding. As an input, DEVSEL# indicates the
response to a VT6305-initiated transaction and is also sampled when decoding
whether to subtractively decode the cycle.
Target Ready.
Asserted when the target is ready for data transfer.
Initiator Ready.
Asserted when the initiator is ready for data transfer.
PCI Bus Request.
Asserted by the bus master to indicate to the bus arbiter that it
wants to use the bus.
PCI Bus Grant.
Asserted to indicate that access to the bus is granted.
Initialization Device Select.
IDSEL is used as a chip select during configuration
read and write cycles.
Interrupt A.
An asynchronous signal used to request an interrupt.
Interrupt B.
An asynchronous signal used to request an interrupt.
PCI Clock.
Timing reference for all transactions on the PCI Bus.
Reset.
When detected low, an internal hardware reset is performed. PCIRST#
assertion or deassertion may be asynchronous to PCLK, however, it is recommended
that deassertion be synchronous to guarantee a clean and bounce free edge.
Parity.
A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
Parity Error.
Parity error is asserted when a data parity error is detected.
System Error.
SERR# is pulsed active to indicate a system error condition.
Stop.
Asserted by the target to request the master to stop the current transaction.
FRAME#
25
IO
DEVSEL#
29
IO
TRDY#
IRDY#
PREQ#
28
27
127
IO
IO
O
PGNT#
IDSEL
126
12
I
O
INTA#
INTB#
PCLK
RESET#
122
121
124
123
O
O
I
I
PAR
PERR#
SERR#
STOP#
34
31
32
30
IO
O
O
IO
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