參數(shù)資料
型號(hào)： VT6305
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI 1394 Host Controller
中文描述： 1394主控制器的PCI
文件頁(yè)數(shù)： 22/35頁(yè)
文件大?。?/td> 220K
代理商： VT6305
Revision 0.2
March 10, 2000
-
17-
Register Descriptions
Technologies, Inc.
WeConnect
Memory Offset 34 – Configuration ROM Map............. RW
This register contains the start address within the memory
space that maps to the start address of the 1394 configuration
ROM. Only 32-bit word reads to the first 1K bytes of the
configuration ROM will map to memory space.(all other
transactions to this space will be rejected with an
“ack_type_error”). The system address of the configuration
ROM must start on a 1K-byte boundary. The first five 32-bit
words of the configuration ROM space are mapped to the
configuration ROM header and Bus Info Block, so the first
five registers addressed by this register are not used. This
register must be set to a valid address prior to setting the “HC
Control” register “l(fā)ink enable” bit.
31-10 Configuration ROM Address
.................default = 0
Read requests to 1394 offsets FFFF F000 0400
through FFFF F000 03FC have the low-order 10 bits
of the offset added to this register to determine the
host memory address of the returned data value.
9-0
Reserved
......................................always reads 0
Memory Offset 38 – Posted Write Address Low ........... RO
31-0 Offset Low
...............................default = undefined
If the “Posted Write Error” bit is set in the Interrupt
Events register, this and the “Posted Write Address
High” register contain the 48 bits of the 1394
destination offset of the write request that resulted in
the PCI error.
Memory Offset 3C – Posted Write Address High .......... RO
31-16 Source ID
...............................default = undefined
The Bus Number and Node Number of the node
which has issued the failed write request.
15-0 Offset High
...............................default = undefined
If the “Posted Write Error” bit is set in the Interrupt
Events register, this and the “Posted Write Address
Low” register contain the 48 bits of the 1394
destination offset of the write request that resulted in
the PCI error.
Memory Offset 40 – Vendor ID ...................................... RO
31-0 Vendor ID
.................................always reads TBD
HC Control Registers
The following two registers are a “set / clear” register pair.
Writing to the “Set” register address sets selected bits in the
control register where the written bit value is 1. Writing to
the “Clear” register address clears selected bits in the control
register where the written bit value is 1. Reading from either
address returns the contents of the control register.
Memory Offset 50 (Set), 54 (Clear) – HC Control ........ RW
31-20 Reserved
......................................always reads 0
19
Link Power Status
0
Prohibit Link to PHY Communications..... def
1
Permit Link to PHY Communications (link
can use LREQs to perform PHY reads and
writes).
This bit has no effect on “Link On” status for the
node (see Link Enable status below). Both software
and hardware resets clear this bit.
18
Posted Write Enable
.................default = undefined
0
All writes return “ack_pending”
1
Enable 2-deep posted write queue
Software should only change this bit when “Link
Enable” is 0.
17
Link Enable
0
Disable packets from being transmitted,
received, or processed...........................default
1
Enable packets to be transmitted, received,
and processed
Both software and hardware resets clear this bit.
Software should not set this bit until the
Configuration ROM mapping register is valid.
16
Soft Reset
When set, all on-chip 1394 states are reset, all FIFOs
are flushed, and all registers are set to their hardware
reset (default) values unless otherwise specified. PCI
configuration registers are not affected. Hardware
clears this bit automatically when the reset is
complete (it reads 1 while the reset is in progress).
15-0 Reserved
......................................always reads 0
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