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參數(shù)資料
| 型號： | VT6305 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI 1394 Host Controller |
| 中文描述： | 1394主控制器的PCI |
| 文件頁數(shù)： | 20/35頁 |
| 文件大?。?/td> | 220K |
| 代理商： | VT6305 |
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Revision 0.2
March 10, 2000
-
15-
Register Descriptions
Technologies, Inc.
WeConnect
Autonomous CSR Resources
The VT6305 implements the 1394 “Compare-and-Swap” bus
management registers, the Configuration ROM Header, and
the “Bus Info Block”. It also allows access to the first 1K
bytes of the configuration ROM.
Atomic compare-and-swap transactions, when accessed from
the 1394 bus, are autonomous without software intervention.
To access these bus management resource registers via the
PCI bus, the software first loads the CSR Data register with a
new data value to be loaded, then it loads the CSR Compare
register with the expected value. Finally, it writes the CSR
Control register with the selected value of the resource. This
initiates a compare-and-swap operation. When complete, the
CSR Control register “done” bit will be set and the CSR Data
register will contain the value of the selected resource prior to
the host-initiated compare-and-swap operation.
Bus Management CSR Registers
1394 requires certain 1394 bus management resource
registers to be accesssible only via 32-bit read and 32-bit lock
(compare-and-swap) transactions. These special bus
management resource registers are implemented on-chip:
CSR
Select
00
01
10 Channels Available Hi FFFF FFFF
18 Channels Available Lo FFFF FFFF
Hardware or
Bus Reset
0000 003F
0000 1333
CSR Address
FFFF F000 021C
FFFF F000 0220
FFFF F000 0224
FFFF F000 0228
Register Name
Bus Manager ID
Bandwidth Available
CSR Address FFFF F000 021C – Bus Manager ID....... RW
31-6 Reserved
......................................always reads 0
5-0
Bus Manager ID
.................................default = 3Fh
CSR Address FFFF F000 0220 – Bandwidth Available RW
31-13 Reserved
......................................always reads 0
12-0 Bandwidth Available
......................default = 1333h
CSR Address FFFF F000 0224 – Channels Avail Hi .... RW
7-0
Reserved
......................................always reads 0
CSR Address FFFF F000 0228 – Channels Avail Lo .... RW
7-0
Reserved
......................................always reads 0
Memory Offset C – CSR Data ....................................... RW
31-0 CSR Data
..............................default = undefined
Data to be stored if comparison is successful.
Memory Offset 10 – CSR Compare Data ...................... RW
31-0 CSR Compare Data
..................default = undefined
Data to be compared with existing value of CSR
resource.
Memory Offset 14 – CSR Control ................................. RW
31
CSR Done
............................................default = 1
Set when a compare-swap operation is completed.
Reset whenever this register is written.
30-2 Reserved
......................................always reads 0
1-0
CSR Resource Select
.................default = undefined
00 Bus Manager ID
01 Bandwidth Available
10 Channels Available Hi
11 Channels Available Lo
Memory Offset 18 – Configuration ROM Header ........ RW
31-24 Bus Info Block Length
............................default = 0
Length of the Bus Information Block in doublewords
23-16 CRC Length
............................................default = 0
Length of the block protected by the CRC (a value of
4 indicates that the CRC only protects the
configuration ROM header).
15-0 ROM CRC Value
Default value loaded from GUID ROM if present
(default is undefined if GUID ROM is not present).
Must be set prior to setting the “HC Control” register
“Link Enable” bit.
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