參數(shù)資料
型號： VT6305
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI 1394 Host Controller
中文描述： 1394主控制器的PCI
文件頁數(shù)： 31/35頁
文件大?。?/td> 220K
代理商： VT6305
Revision 0.2
March 10, 2000
-
26-
Register Descriptions
Technologies, Inc.
WeConnect
Isochronous Transmit Context Registers
Offset 200 (Set), 204 (Clr) – Isoch Xmit Context 0........ RW
Offset 210 (Set), 214 (Clr) – Isoch Xmit Context 1........ RW
Offset 220 (Set), 224 (Clr) – Isoch Xmit Context 2........ RW
Offset 230 (Set), 234 (Clr) – Isoch Xmit Context 3........ RW
These registers are the Context Control registers for
Isocchronous Transmit Contexts 0-3. Each context consists
of two registers: a Command Pointer and a Context Control
register. The Command Pointer is used by software to tell the
controller where the context program begins. The Context
Control register controls the context’s behavior and indicates
current status. The bit layout for the Context Control
registers is given below:
31-30 Reserved
29
Cycle Match Enable
In general, when set to one the context will begin
running only when the 13-bit “Cycle Match” field
matches the 13-bit “Cycle Count” in the Cycle Start
packet. The effects of this bit however are impacted
by the values of other bits in this register. Once the
context becomes active, this bit is cleared
automatically by the chip.
28-16 Cycle Match
Contains a 13-bit value corresponding to the 13-bit
“Cycle Count” field. If the “Cycle Match Enable”
bit is set, this ITDMA context will become enabled
for transmits when the bus cycle time “Cycle Count”
value equals the value in this field.
15
Run
This bit is set and cleared by software to enable
descriptor processing for a context. The chip will
clear this bit automatically on a hardware or software
reset. Before software sets this bit, the active bit
must be clear and the Command Pointer register for
the context must contain a valid descriptor block
address and a Z value that is appropriate for the
descriptor block address.
Software may stop the chip from further processing
of a context by clearing this bit. When cleared, the
chip will stop processing of the context in a manner
that will not impact the operation of any other
context or DMA controller. This may require a
significant amount of time. If software clears a run
bit while the chip is processing a packet for the
context, it will continue to receive or transmit the
packet and update the descriptor status. It will then
stop at the conclusion of that packet.
Clearing the bit may have other side effects that are
DMA controller dependent. This is described in the
sections that cover each of the DMA controllers.
14-13 Reserved
......................................always reads 0
......................................always reads 0
12
Wake
When software adds to a list of descriptors for a
context, the chip may have already read the
descriptor that was at the end of the list before it was
updated. This bit provides a semaphore to indicate
that the list may have changed.
If the chip had fetched a descriptor and the indicated
branch address had a Z value of zero, it will reread
the pointer value when the wake bit is set. If, on the
reread, the Z value is still zero, then the end of the
list has been reached and the chip will clear the
active bit. If, however, the Z value is now non-zero,
the chip will continue processing. If the wake bit is
set while the chip is active and has a Z value of non-
zero, it takes no special action.
The chip will clear this bit before it reads or rereads
a descriptor. The wake bit should not be set while
the run bit is zero.
Dead
............................................default = 0
This bit is set by the chip to indicate a fatal error in
processing a descriptor. When set, the active bit is
cleared. This bit is cleared when software clears the
run bit or on a hardware or software reset.
Active
............................................default = 0
This bit is set by the chip when software sets the run
bit or sets the wake bit while the run bit is set. The
chip will clear this bit:
1)
when a branch is indicated by a descriptor but
the Z value of the branch address is 0
2)
when software clears the run bit and the chip
has reached a safe stopping point
3)
while the dead bit is set
4)
after a hardware or software reset
When this bit is cleared and the run bit is clear, the
chip will set the Interrupt Event bit for the context.
Reserved
......................................always reads 0
Ack / Err Code
........................................default = 0
Following an “Output Last” command, the received
“Ack Code” or “Event Error Code” is indicated in
this field. Possible values are: “Ack Complete”,
“Ack Pending”, Ack Busy X”, “Ack Data Error”,
“Ack Type Error”, “Event Tcode Error”, “Event
Missing Ack”, “Event Underrun”, “Event Descriptor
Read”, “Event Data Read”, “Event Timeout”, “Event
Flushed”, and “Event Unknown” (see “Table 3.
Packet Event Codes” on the previous page for
descriptions and values for these codes).
............................................default = 0
11
10
9-5
4-0
Offset 20C – Isoch Xmit Context 0 Command Ptr ........ RW
Offset 21C – Isoch Xmit Context 1 Command Ptr ........ RW
Offset 22C – Isoch Xmit Context 2 Command Ptr ........ RW
Offset 23C – Isoch Xmit Context 3 Command Ptr ........ RW
相關(guān)PDF資料
PDF描述
VT6516 16/12 PORT 10/1000 ASE T/TX
VT70A144
VT74A451
VT74A901
VT77A142
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VT6508 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8 RMII PORTS OF 10/100BASE-T/TX ETHERNET SWITCH CONTROLLER
VT6510B 制造商:VIA 功能描述:
VT6516 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16/12 PORT 10/1000 ASE T/TX
VT-6-6 制造商:Panduit Corp 功能描述:BOLT TERM 70MM 57MM - Bulk 制造商:Panduit Corp 功能描述:Bolt Terminal 70mm 57mm
VT6J1 制造商:ROHM 制造商全稱:Rohm 功能描述:1.2V Drive Pch + Pch MOSFET
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*