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參數(shù)資料
| 型號(hào)： | VT6305 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI 1394 Host Controller |
| 中文描述： | 1394主控制器的PCI |
| 文件頁數(shù)： | 24/35頁 |
| 文件大?。?/td> | 220K |
| 代理商： | VT6305 |
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Revision 0.2
March 10, 2000
-
19-
Register Descriptions
Technologies, Inc.
WeConnect
Interrupt Registers
Memory Offset 80 (Set), 84 (Clear) – Interrupt Events RW
31-27 Reserved
......................................always reads 0
26
PHY Register Data Recieved
PHY register data byte received (data byte not sent
when register 0 received)
25
Cycle Too Long
More than 115 usec (but not more than 120 usec)
elapsed between the start of sending a cycle start
packet and the end of a subaction gap.
24
Unrecoverable Error
Error encountered that has forced the chip to stop
operations of any or all subunits (e.g., when a DMA
context sets its “ContextControl.Dead” bit)
23
Cycle Inconsistent
Cycle start received with a cycle count different from
the value in the “Cycle Timer” register
22
Cycle Lost
Expected cycle start not received (cycle start not
received immediately after the first subaction gap
after the “Cycle Sync” event or arbitration reset gap
detected after a “Cycle Sync” event without an
intervening cycle start).
21
Cycle 64 Seconds Interrupt
Bit 7 of the “Cycle Seconds Counter” has changed.
20
Cycle Synch Interrupt
New isochronous cycle started (least significant bit
of the cycle count toggled).
19
PHY Requested Interrupt
The PHY has requested an interrupt using a status
transfer.
18
Reserved
......................................always reads 0
17
Bus Reset Entered
The Phy has entered bus reset mode.
16
Self-ID Complete
Self-ID packet stream received.
15-10 Reserved
......................................always reads 0
9
Lock Response Error
Lock response sent to a serial bus register in
response to a lock request but no “ack_complete”
received.
8
Posted Write Error
A host bus error occurred while the chip was trying
to write a 1394 write request (which had already
been given an “ack_complete”) into system memory.
7
Isochronous ReceiveDMA Complete
One or more Isochronous receive contexts have
generated an interrupt (one or more bits have been
set in the “Isochronous Receive Interrupt Event”
register masked by the “Isochronous Receive
Interrupt Mask” register).
Isochronous Transmit DMA Complete
One or more Isochronous transmit contexts have
generated an interrupt (one or more bits have been
set in the “Isochronous Transmit Interrupt Event”
register masked by the “Isochronous Transmit
Interrupt Mask” register).
6
5
Response Packet Sent
A packet was sent to an asynchronous receive
response context buffer.
Receive Packet Sent
A packet was sent to an asynchronous receive
request context buffer.
4
3
Async Receive Response DMA Complete
Conditionally set upon completion of an ARDMA
Response context command descriptor.
Async Receive Request DMA Complete
Conditionally set upon completion of an ARDMA
Request context command descriptor.
2
1
Async Response Transmit DMA Complete
Conditionally set upon completion of an ATDMA
Response command.
Async Request Transmit DMA Complete
Conditionally set upon completion of an ATDMA
Request command.
0
Memory Offset 88 (Set), 8C (Clear) – Interrupt Mask . RW
The bits in this register (except for the Master Interrupt
Enable bit in bit-31) correspond to the bits in the Interrupt
Event register above. Zeros in these bits prevent the
corresponding interrupt condition from generating an
interrupt. Bits are set in the mask register by writing one bits
to the “Set” address and cleared by writing one bits to the
“Clear” address. The current value of the mask bits may be
read from either address.
31
Master Interrupt Enable
0
Disable All Interrupt Events.................default
1
Generate interrupts per mask bits 0-26
30-27 Reserved
......................................always reads 0
26-0 Interrupt Mask
.........................default = undefined
(see Interrupt Event register)
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