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參數(shù)資料
| 型號： | VT6305 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI 1394 Host Controller |
| 中文描述： | 1394主控制器的PCI |
| 文件頁數(shù)： | 25/35頁 |
| 文件大小： | 220K |
| 代理商： | VT6305 |
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Revision 0.2
March 10, 2000
-
20-
Register Descriptions
Technologies, Inc.
WeConnect
Offset 90 (Set), 94 (Clear) – Iso Xmit Interrupt Events RW
31-4 Reserved
......................................always reads 0
3-0
Isochronous Transmit Context
.default = undefined
An interrupt is generated by an isochronous transmit
context if an “Output Last DMA” command
completes and its “i” bits are set to “interrupt
always”. Software clears the bits in this register by
writing one bits to the “Clear” address. Bits in this
register will only get set to one if the corresponding
bits in the mask register are set to one.
Offset 98 (Set), 9C (Clear) – Iso Xmit Interrupt Mask RW
31-4 Reserved
......................................always reads 0
3-0
Iso Transmit Context Mask
.......default = undefined
Setting bits in this register enables interrupts to be
generated by the corresponding isochronous transmit
context
Offset A0 (Set), A4 (Clear) – Iso Rcv Interrupt Events. RW
31-4 Reserved
......................................always reads 0
3-0
Isochronous Receive Context
...default = undefined
An interrupt is generated by an isochronous receive
context if an “Input Last DMA” command completes
and its “i” bits are set to “interrupt always”.
Software clears the bits in this register by writing
one bits to the “Clear” address. Bits in this register
will only get set to one if the corresponding bits in
the mask register are set to one.
Offset A8 (Set), AC (Clear) – Iso Rcv Interrupt Mask . RW
31-4 Reserved
......................................always reads 0
3-0
Iso Receive Context Mask
.........default = undefined
Setting bits in this register enables interrupts to be
generated by the corresponding isochronous receive
context
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